{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T10:31:34Z","timestamp":1725445894280},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,10]]},"DOI":"10.1109\/aiccsa.2018.8612877","type":"proceedings-article","created":{"date-parts":[[2019,1,18]],"date-time":"2019-01-18T01:26:29Z","timestamp":1547774789000},"page":"1-5","source":"Crossref","is-referenced-by-count":0,"title":["Evaluating Cache Power Dissipation Across Different Process Technologies"],"prefix":"10.1109","author":[{"given":"Shereen","family":"Ismail","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Amal","family":"Ahmad","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mohammed","family":"Awad","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mohammad Abdul","family":"Jawad","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2015.74"},{"year":"0","key":"ref11"},{"key":"ref12","first-page":"22","article-title":"CACTI 6.0: A tool to model large caches","author":"muralimanohar","year":"2009","journal-title":"HP Laboratories"},{"journal-title":"International Technology Roadmap for Semiconductors","year":"2005","key":"ref13"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.11"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1016\/j.suscom.2013.11.001"},{"key":"ref3","first-page":"1","article-title":"Toward cache-friendly hardware accelerators","author":"shao","year":"0","journal-title":"2015 In HPCA Sensors and Cloud Architectures Workshop (SCAW)"},{"journal-title":"Cache Power Optimization Using Multiple Voltage Supplies to Exploit Read\/Write Asymmetry","year":"2017","author":"yan","key":"ref6"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/IGCC.2013.6604475"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228521"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228406"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISOCC.2015.7401759"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1016\/j.suscom.2013.11.001"},{"key":"ref9","first-page":"143","article-title":"Technology comparison for large last-level caches (L 3 Cs): Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM. In High Performance Computer Architecture (HPCA2013)","author":"chang","year":"2013","journal-title":"19th IEEE International Symposium on"}],"event":{"name":"2018 IEEE\/ACS 15th International Conference on Computer Systems and Applications (AICCSA)","start":{"date-parts":[[2018,10,28]]},"location":"Aqaba","end":{"date-parts":[[2018,11,1]]}},"container-title":["2018 IEEE\/ACS 15th International Conference on Computer Systems and Applications (AICCSA)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8612460\/8612765\/08612877.pdf?arnumber=8612877","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,27]],"date-time":"2022-01-27T00:10:41Z","timestamp":1643242241000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8612877\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,10]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/aiccsa.2018.8612877","relation":{},"subject":[],"published":{"date-parts":[[2018,10]]}}}