{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T10:10:36Z","timestamp":1730196636276,"version":"3.28.0"},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/apccas.2002.1114930","type":"proceedings-article","created":{"date-parts":[[2003,6,26]],"date-time":"2003-06-26T01:03:42Z","timestamp":1056589422000},"page":"171-176","source":"Crossref","is-referenced-by-count":0,"title":["An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions"],"prefix":"10.1109","volume":"1","author":[{"given":"Y.","family":"Miyaoka","sequence":"first","affiliation":[]},{"given":"J.","family":"Choi","sequence":"additional","affiliation":[]},{"given":"N.","family":"Togawa","sequence":"additional","affiliation":[]},{"given":"M.","family":"Yanagisawa","sequence":"additional","affiliation":[]},{"given":"T.","family":"Ohtsuki","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","first-page":"483","article-title":"PEAS-I: A hardware\/software codesign system for ASIP development","volume":"e77 a","author":"sato","year":"1994","journal-title":"IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences"},{"key":"ref11","article-title":"A hardware\/software cosynthesis system for digital signal processor cores","volume":"e82 a","author":"togawa","year":"1999","journal-title":"IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/40.526921"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/92.831437"},{"key":"ref4","first-page":"629","article-title":"Future directions of media processors","volume":"e81 c","author":"ishiwata","year":"1998","journal-title":"IEICE Trans on Electronics"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/40.848475"},{"key":"ref6","first-page":"1994","author":"lapsley","year":"0","journal-title":"Processor Fundamentals Architectures and Features Berkeley Design Technology Inc"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2000.878319"},{"key":"ref8","first-page":"83","article-title":"Flexible hardware model database management system: implementation and effectiveness","author":"morifuji","year":"1997","journal-title":"Proc of the and System Integration Mixed Technologies (SASIM1'97)"},{"journal-title":"Digital Signal Process","year":"1995","author":"madisetti","key":"ref7"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/40.848472"},{"key":"ref1","first-page":"1760","article-title":"COACH: A computer aided design tool for computer architectures","volume":"e76 a","author":"akaboshi","year":"1993","journal-title":"IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/40.526924"}],"event":{"name":"APCCAS. Asia-Pacific Conference on Circuits and Systems","acronym":"APCCAS-02","location":"Bali, Indonesia"},"container-title":["Asia-Pacific Conference on Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8182\/24591\/01114930.pdf?arnumber=1114930","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,13]],"date-time":"2017-03-13T21:21:26Z","timestamp":1489440086000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1114930\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/apccas.2002.1114930","relation":{},"subject":[]}}