{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T10:10:36Z","timestamp":1730196636989,"version":"3.28.0"},"reference-count":8,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/apccas.2002.1114936","type":"proceedings-article","created":{"date-parts":[[2003,6,25]],"date-time":"2003-06-25T21:03:42Z","timestamp":1056575022000},"page":"199-202","source":"Crossref","is-referenced-by-count":1,"title":["Memory allocation method for indirect addressing with an index register"],"prefix":"10.1109","volume":"1","author":[{"given":"Y.","family":"Kaneko","sequence":"first","affiliation":[]},{"given":"N.","family":"Sugino","sequence":"additional","affiliation":[]},{"given":"A.","family":"Nishihara","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","first-page":"1217","article-title":"DSP Code Optimization utilizing Memory Addressing Operation","volume":"e79 a","author":"sugino","year":"1996","journal-title":"IEICE Trans Fundamentals"},{"key":"ref3","first-page":"395","article-title":"Computational ordering of digital network under the pipeline constraints and its application to compiler for DSPs","author":"sugino","year":"1989","journal-title":"Proc ECCT D '89"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1997.612853"},{"key":"ref5","first-page":"249","article-title":"Improved code optimization method utilizing memory addressing and its application to DSP compiler","author":"sugino","year":"1996","journal-title":"Proc ISCAS 1996"},{"key":"ref8","article-title":"Memory Allocation Method for Indirect Addressing DSPs with &#x00B1;2 Update Operations","volume":"e81 a","author":"kogure","year":"1998","journal-title":"IEICE Trans Fundamentals"},{"key":"ref7","first-page":"617","article-title":"Memory Allocation Method for Indirect Addressing with Index Register","author":"seno","year":"1999","journal-title":"14th Digital Signal Processing Symposium in Japan"},{"key":"ref2","first-page":"327","article-title":"Computational ordering of digital signal processing networks and its application to compilers for signal processors","volume":"j71 a","author":"sugino","year":"1988","journal-title":"IECE Tams"},{"key":"ref1","first-page":"2562","article-title":"DSP Code Optimization Methods Utilizing Addressing Operations at the Codes without Memory Accesses","author":"sugino","year":"1997","journal-title":"IEICE Trans Fundamentals E80-A"}],"event":{"name":"APCCAS. Asia-Pacific Conference on Circuits and Systems","acronym":"APCCAS-02","location":"Bali, Indonesia"},"container-title":["Asia-Pacific Conference on Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8182\/24591\/01114936.pdf?arnumber=1114936","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,13]],"date-time":"2017-03-13T17:37:00Z","timestamp":1489426620000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1114936\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":8,"URL":"https:\/\/doi.org\/10.1109\/apccas.2002.1114936","relation":{},"subject":[]}}