{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T23:22:16Z","timestamp":1729639336193,"version":"3.28.0"},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/apccas.2002.1115250","type":"proceedings-article","created":{"date-parts":[[2003,6,25]],"date-time":"2003-06-25T20:51:07Z","timestamp":1056574267000},"page":"325-330","source":"Crossref","is-referenced-by-count":0,"title":["Gate speed improvement at minimal power dissipation"],"prefix":"10.1109","volume":"2","author":[{"given":"P.","family":"Maurine","sequence":"first","affiliation":[]},{"given":"X.","family":"Michel","sequence":"additional","affiliation":[]},{"given":"N.","family":"Azemard","sequence":"additional","affiliation":[]},{"given":"D.","family":"Auvergne","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/224081.224083"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2001.922060"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-45373-3_13"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/4.736655"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/4.52187"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/43.736183"},{"key":"ref6","article-title":"Computing The Entire Area \/Power Consumption Versus Delay Tradeoff Curve For Gate Sizing With A Piecewise Linear Simulator","volume":"15","author":"berkelaar","year":"96","journal-title":"IEEE Trans on CAD of IC and Sys"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/81.662699"},{"key":"ref8","first-page":"167","article-title":"Transistor Sizing Power Consumption Of CMOS Circuits Under Delay Constraint","author":"borah","year":"0","journal-title":"Intl Symp Low Power Design"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/43.248073"},{"key":"ref2","article-title":"Estimation of Short-Circuit Power Dissipation for Static CMOS Gates","volume":"e79 a","author":"hirata","year":"1996","journal-title":"IEICE Trans Fundamentals"},{"key":"ref1","doi-asserted-by":"crossref","first-page":"468","DOI":"10.1109\/JSSC.1984.1052168","article-title":"Short circuit power dissipation of static CMOS circuitry and its impact on the design of buffer circuits","volume":"sc 19","author":"veendrick","year":"84","journal-title":"IEEE J Solid State Circuits"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/4.126534"}],"event":{"name":"APCCAS. Asia-Pacific Conference on Circuits and Systems","acronym":"APCCAS-02","location":"Bali, Indonesia"},"container-title":["Asia-Pacific Conference on Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8182\/24592\/01115250.pdf?arnumber=1115250","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,15]],"date-time":"2017-06-15T18:45:53Z","timestamp":1497552353000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1115250\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/apccas.2002.1115250","relation":{},"subject":[]}}