{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T09:51:38Z","timestamp":1725529898596},"reference-count":10,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2008,11]]},"DOI":"10.1109\/apccas.2008.4745958","type":"proceedings-article","created":{"date-parts":[[2009,1,16]],"date-time":"2009-01-16T15:24:53Z","timestamp":1232119493000},"page":"53-56","source":"Crossref","is-referenced-by-count":0,"title":["UVeriESD: An ESD verification tool for SoC design"],"prefix":"10.1109","author":[{"given":"K. Kelvin","family":"Hsueh","sequence":"first","affiliation":[]},{"family":"Sin-Hao Ke","sequence":"additional","affiliation":[]},{"given":"Jeffrey","family":"Lee","sequence":"additional","affiliation":[]},{"given":"Elyse","family":"Rosenbaum","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"3","first-page":"465","article-title":"verifyesd: a tool for efficient circuit level esd simulations of mixed-signal ics","author":"baird","year":"2000","journal-title":"EOS\/ESD Symposium Proceedings"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2001.922094"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1007\/BF01386390"},{"key":"1","first-page":"208","article-title":"an automated tool for detecting esd design errors","author":"sinha","year":"1998","journal-title":"EOS\/ESD Symposium Proceedings"},{"year":"0","key":"7"},{"key":"6","first-page":"603","article-title":"chip-level esd simulation for fail detection and design guidance","author":"druen","year":"2004","journal-title":"IEEEIRPS"},{"key":"5","first-page":"96","article-title":"automatic layout based verification of electrostatic discharge paths","author":"ngan","year":"2001","journal-title":"EOS\/ESD Symposium Proceedings"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2004.1283713"},{"year":"0","key":"9"},{"key":"8","first-page":"396","article-title":"esd simulation using extracted netlist to validate esd design improvement","author":"conner","year":"2007","journal-title":"1st International ESD Workshop"}],"event":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","start":{"date-parts":[[2008,11,30]]},"location":"Macao, China","end":{"date-parts":[[2008,12,3]]}},"container-title":["APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4723905\/4745943\/04745958.pdf?arnumber=4745958","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,17]],"date-time":"2017-03-17T15:58:10Z","timestamp":1489766290000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4745958\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,11]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/apccas.2008.4745958","relation":{},"subject":[],"published":{"date-parts":[[2008,11]]}}}