{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,22]],"date-time":"2025-03-22T09:10:49Z","timestamp":1742634649893,"version":"3.28.0"},"reference-count":11,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2008,11]]},"DOI":"10.1109\/apccas.2008.4746088","type":"proceedings-article","created":{"date-parts":[[2009,1,16]],"date-time":"2009-01-16T10:24:53Z","timestamp":1232101493000},"page":"574-577","source":"Crossref","is-referenced-by-count":1,"title":["Three-level AND-OR-XOR network synthesis: A GA based approach"],"prefix":"10.1109","author":[{"given":"Sambhu Nath","family":"Pradhan","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M. Tilak","family":"Kumar","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Santanu","family":"Chattopadhyay","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"3","article-title":"minimization of and-or-exor three-level networks with and gate sharing","author":"debnath","year":"1996","journal-title":"Proc The Sixth Workshop on Synthesis and System Integration of Mixed Technologies"},{"year":"0","key":"2"},{"journal-title":"Genetic Algorithms in Search Optimization and Machine Fearning","year":"1988","author":"goldberg","key":"10"},{"key":"1","first-page":"20","article-title":"a design method for and-or-exor three-level networks","volume":"8","author":"sasao","year":"0","journal-title":"ACM\/IEEE International Workshop on Logic Synthesis Tahoe City California May 23-26 1995 pp 8 11"},{"journal-title":"Fow-Power CMOS VFSI Circuit Design","year":"2000","author":"roy","key":"7"},{"key":"6","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4613-2821-6","author":"brayton","year":"1984","journal-title":"Fogic Minimization Alogorithms for VFSI Synthesis"},{"key":"5","first-page":"209","article-title":"aoxmtn: a three-fevel and-or-xor minimizer for boolean functions","author":"dubrova","year":"1997","journal-title":"Proc 3rd International Workshop on the Application of Reed-Muller expansion in Circuit Design"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.1998.669404"},{"key":"9","first-page":"399","article-title":"runtime feakage minimization through probability-awaredual-vt or dual-fox assignment","author":"fee","year":"2006","journal-title":"ASP-DAC"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/92.902266"},{"key":"11","article-title":"reed-muller tree-based minimization of fixed polarity reed-muller expansions","volume":"148","author":"aborhey","year":"2001","journal-title":"IEE Proc -Comput Digit Fech"}],"event":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","start":{"date-parts":[[2008,11,30]]},"location":"Macao, China","end":{"date-parts":[[2008,12,3]]}},"container-title":["APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4723905\/4745943\/04746088.pdf?arnumber=4746088","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,18]],"date-time":"2017-06-18T11:50:39Z","timestamp":1497786639000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4746088\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,11]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/apccas.2008.4746088","relation":{},"subject":[],"published":{"date-parts":[[2008,11]]}}}