{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T00:57:40Z","timestamp":1729645060616,"version":"3.28.0"},"reference-count":12,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2008,11]]},"DOI":"10.1109\/apccas.2008.4746265","type":"proceedings-article","created":{"date-parts":[[2009,1,16]],"date-time":"2009-01-16T15:24:53Z","timestamp":1232119493000},"page":"1296-1299","source":"Crossref","is-referenced-by-count":2,"title":["A low complexity modulo 2&lt;sup&gt;n&lt;\/sup&gt;+1 squarer design"],"prefix":"10.1109","author":[{"given":"Ramya","family":"Muralidharan","sequence":"first","affiliation":[]},{"given":"Chip-Hong","family":"Chang","sequence":"additional","affiliation":[]},{"given":"Ching-Chuen","family":"Jong","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2007.890623"},{"key":"2","doi-asserted-by":"crossref","first-page":"211","DOI":"10.1049\/ip-g-2.1993.0034","article-title":"area-efficient diminished-1 multiplier for fermat number-theoretic transform","volume":"140","author":"sunder","year":"1993","journal-title":"Circuits Devices and Systems IEE Proceedings G"},{"journal-title":"Computer Arithmetic-Agorithms and Hardware Designs","year":"2002","author":"parhami","key":"10"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/4.278352"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cdt:20055037"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2005.63"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2002.1146705"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/TASSP.1976.1162834"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/82.996056"},{"key":"8","first-page":"614","article-title":"a new modulo 2n+1 multiplier","author":"wrzyszcz","year":"1993","journal-title":"Proc IEEE Int Conf of Computer Design (ICCD'93)"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cdt:20060026"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/APCCAS.2006.342349"}],"event":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","start":{"date-parts":[[2008,11,30]]},"location":"Macao, China","end":{"date-parts":[[2008,12,3]]}},"container-title":["APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4723905\/4745943\/04746265.pdf?arnumber=4746265","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,10,14]],"date-time":"2020-10-14T14:51:16Z","timestamp":1602687076000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/4746265"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,11]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/apccas.2008.4746265","relation":{},"subject":[],"published":{"date-parts":[[2008,11]]}}}