{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,21]],"date-time":"2025-06-21T22:23:45Z","timestamp":1750544625666},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2008,11]]},"DOI":"10.1109\/apccas.2008.4746382","type":"proceedings-article","created":{"date-parts":[[2009,1,16]],"date-time":"2009-01-16T10:24:53Z","timestamp":1232101493000},"page":"1763-1766","source":"Crossref","is-referenced-by-count":16,"title":["A proposed FPGA-based parallel architecture for matrix multiplication"],"prefix":"10.1109","author":[{"given":"Syed Manzoor","family":"Qasim","sequence":"first","affiliation":[]},{"given":"Shuja Ahmad","family":"Abbasi","sequence":"additional","affiliation":[]},{"given":"Bandar","family":"Almashary","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2002.801622"},{"key":"13","first-page":"225","article-title":"energy efficient signal processing using fpgas","author":"choi","year":"2003","journal-title":"Proc ACM Int l Symp Field Programmable Gate Arrays"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2004.1333283"},{"key":"11","first-page":"534","article-title":"energy efficient matrix multiplication on fpgas","author":"jang","year":"2000","journal-title":"Proc Intl Conf Field Programmable Logic and Appl"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1117\/12.455487"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2000.951667"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cdt:20070012"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cdt:20045086"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1145\/503048.503072"},{"key":"7","first-page":"93","article-title":"area and time efficient implementations of matrix multiplication on fpgas","author":"jang","year":"2002","journal-title":"Proc of IEEE Int Conf on Field Programmable Technology"},{"key":"6","doi-asserted-by":"crossref","first-page":"101","DOI":"10.1007\/3-540-44687-7_11","article-title":"accelerating matrix product on reconfigurable hardware for signal processing","author":"amira","year":"2001","journal-title":"Proc Intl Conf Field Programmable Logic and Appl"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1998.707894"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/SIPS.2002.1049688"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/CAMP.2003.1598160"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2005.859562"}],"event":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","start":{"date-parts":[[2008,11,30]]},"location":"Macao, China","end":{"date-parts":[[2008,12,3]]}},"container-title":["APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4723905\/4745943\/04746382.pdf?arnumber=4746382","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,18]],"date-time":"2017-06-18T11:50:39Z","timestamp":1497786639000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4746382\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,11]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/apccas.2008.4746382","relation":{},"subject":[],"published":{"date-parts":[[2008,11]]}}}