{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,6]],"date-time":"2026-03-06T04:34:49Z","timestamp":1772771689094,"version":"3.50.1"},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,12]]},"DOI":"10.1109\/apccas.2010.5774875","type":"proceedings-article","created":{"date-parts":[[2011,5,27]],"date-time":"2011-05-27T13:30:45Z","timestamp":1306503045000},"page":"919-922","source":"Crossref","is-referenced-by-count":11,"title":["Star-type architecture with low transmission latency for a 2D mesh NOC"],"prefix":"10.1109","author":[{"given":"Kuan-Ju","family":"Chen","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chin-Hung","family":"Peng","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Feipei","family":"Lai","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/2.191995"},{"key":"ref11","article-title":"Evaluation of Routing Algorithms on Mesh Based NoCs","author":"mello","year":"2004","journal-title":"Faculdade de Informatica"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2009.5090700"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2002.1176258"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ICM.2006.373261"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/378239.379048"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250681"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2007.3"},{"key":"ref8","author":"lee","year":"2008","journal-title":"Low Transmission Latency Method for 2D-mesh NoC Architecture"},{"key":"ref7","first-page":"262","article-title":"Mesh-Tree Architecture for Network-on-Chip Design","author":"yuan-long","year":"2007","journal-title":"Innovative Computing Information and Control 2007 ICICIC ‘07 Second International Conference"},{"key":"ref2","doi-asserted-by":"crossref","first-page":"1025","DOI":"10.1109\/TC.2005.134","article-title":"Performance evaluation and design trade-offs for network-on-chip interconnect architectures","volume":"54","author":"pratim","year":"2005","journal-title":"Computers IEEE Transactions"},{"key":"ref1","doi-asserted-by":"crossref","first-page":"81","DOI":"10.1016\/j.sysarc.2003.07.005","article-title":"Packetization and routing analysis of on-chip multiprocessor networks","volume":"50","author":"ye","year":"2004","journal-title":"J Syst Archit"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2003.1213311"}],"event":{"name":"APCCAS 2010-2010 IEEE Asia Pacific Conference on Circuits and Systems","location":"Kuala Lumpur, Malaysia","start":{"date-parts":[[2010,12,6]]},"end":{"date-parts":[[2010,12,9]]}},"container-title":["2010 IEEE Asia Pacific Conference on Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5767825\/5774732\/05774875.pdf?arnumber=5774875","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,19]],"date-time":"2017-06-19T20:54:21Z","timestamp":1497905661000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5774875\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,12]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/apccas.2010.5774875","relation":{},"subject":[],"published":{"date-parts":[[2010,12]]}}}