{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T18:13:43Z","timestamp":1729620823186,"version":"3.28.0"},"reference-count":10,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,12]]},"DOI":"10.1109\/apccas.2010.5774961","type":"proceedings-article","created":{"date-parts":[[2011,5,27]],"date-time":"2011-05-27T17:30:45Z","timestamp":1306517445000},"page":"616-619","source":"Crossref","is-referenced-by-count":1,"title":["A hybrid architecture for efficient FPGA-based implementation of multilayer neural network"],"prefix":"10.1109","author":[{"given":"Zhen","family":"Lin","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yiping","family":"Dong","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yan","family":"Li","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Takahiro","family":"Watanabe","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","article-title":"FPGA implementation of neural networks - a survey of a decade of progress","author":"zhu","year":"2003","journal-title":"Proc FPL’03"},{"key":"ref3","doi-asserted-by":"crossref","first-page":"945","DOI":"10.1016\/j.engappai.2004.08.011","article-title":"Artificial Neural Network: A Review of Commercial Hardware","volume":"17","author":"morgado","year":"2004","journal-title":"Engineering application of artificial intelligence"},{"year":"0","key":"ref10"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TPEL.2006.882420"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TNN.2002.806955"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TNN.2007.891626"},{"key":"ref7","article-title":"NeuroFPGA - Implementation artificial neural networks on programmable logic devices","author":"ferrer","year":"2004","journal-title":"Proc DATE’04"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TNN.2005.852237"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISDA.2008.333"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TIE.1999.807982"}],"event":{"name":"APCCAS 2010-2010 IEEE Asia Pacific Conference on Circuits and Systems","start":{"date-parts":[[2010,12,6]]},"location":"Kuala Lumpur, Malaysia","end":{"date-parts":[[2010,12,9]]}},"container-title":["2010 IEEE Asia Pacific Conference on Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5767825\/5774732\/05774961.pdf?arnumber=5774961","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,20]],"date-time":"2017-06-20T00:54:22Z","timestamp":1497920062000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5774961\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,12]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/apccas.2010.5774961","relation":{},"subject":[],"published":{"date-parts":[[2010,12]]}}}