{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T05:39:30Z","timestamp":1729661970285,"version":"3.28.0"},"reference-count":27,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,12]]},"DOI":"10.1109\/apccas.2012.6419085","type":"proceedings-article","created":{"date-parts":[[2013,1,30]],"date-time":"2013-01-30T22:53:42Z","timestamp":1359586422000},"page":"515-518","source":"Crossref","is-referenced-by-count":1,"title":["Multifunction RNS modulo (2<sup>n<\/sup>±1) multipliers based on modified booth encoding"],"prefix":"10.1109","author":[{"given":"Tso-Bing","family":"Juang","sequence":"first","affiliation":[]},{"given":"Jian-Hao","family":"Huang","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"crossref","first-page":"897","DOI":"10.1109\/TCSII.2008.923413","article-title":"VLSI design of diminished-one modulo - 2n +1 adder using circular carry selection","volume":"55","author":"lin","year":"2008","journal-title":"IEEE Transactions on Circuits and Systems II Express Briefs"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cdt:20060026"},{"key":"18","first-page":"376","article-title":"Design of an area-efficient weighted modulo 2n+1 multipliers","author":"juang","year":"2009","journal-title":"Proc Application and Innovation of Prototypes and Circuits"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2002.1146705"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2005.63"},{"key":"13","doi-asserted-by":"crossref","first-page":"211","DOI":"10.1049\/ip-g-2.1993.0034","article-title":"area-efficient diminished-1 multiplier for fermat number-theoretic transform","volume":"140","author":"sunder","year":"1993","journal-title":"Circuits Devices and Systems IEE Proceedings G"},{"key":"14","doi-asserted-by":"crossref","first-page":"158","DOI":"10.1109\/ARITH.1999.762841","article-title":"Efficient VLSI implementation of modulo (2n?1) addition and multiplication","author":"zimmerman","year":"1999","journal-title":"Proc IEEE Symposium on Computer Arithmetic"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2008.2008507"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/TASSP.1976.1162834"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2010.2040302"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2009.2015352"},{"key":"22","first-page":"57","article-title":"Unified approach to the design of modulo-(2n \ufffd 1) adders based on signed-LSB representation of residues","author":"jaberipur","year":"2009","journal-title":"Proc 11th IEEE Symp Computer Arithmetic"},{"key":"23","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1973.223639"},{"key":"24","doi-asserted-by":"publisher","DOI":"10.1109\/TEC.1960.5219822"},{"key":"25","doi-asserted-by":"publisher","DOI":"10.1142\/S0218126612500272"},{"key":"26","first-page":"637","article-title":"Modified Booth 1's complement and modulo 2n-1 multiplers","volume":"2","author":"efstathiou","year":"2000","journal-title":"Proc of the 7th IEEE International Conference on Electrnoics Circutis and Systems (ICECS)"},{"key":"27","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2080330"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2000.951651"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1049\/el:20020192"},{"key":"10","first-page":"364","article-title":"Implementation of RSA algorithm based on RNS montgomery multiplication","volume":"2162","author":"nozaki","year":"2001","journal-title":"Proc of the 3rd International Workshop on Cryptographic Hardware and Embedded Systems Lecture Notes in Computer Science"},{"journal-title":"Residue Number System Arithmetic Modern Applications in Digital Signal Processing","year":"1986","author":"soderstrand","key":"1"},{"key":"7","first-page":"63","article-title":"Fast RNS FPL-based communications receiver design and implementation","volume":"2438","author":"ramirez","year":"2002","journal-title":"Proc of the 12th International Conference on Field Programmable Logic Lecture Notes in Computer Science"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2007.378155"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/ACSSC.2001.987709"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2001.921068"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/TWC.2004.833509"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/TVT.2002.804850"}],"event":{"name":"APCCAS 2012-2012 IEEE Asia Pacific Conference on Circuits and Systems","start":{"date-parts":[[2012,12,2]]},"location":"Kaohsiung, Taiwan","end":{"date-parts":[[2012,12,5]]}},"container-title":["2012 IEEE Asia Pacific Conference on Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6412846\/6418954\/06419085.pdf?arnumber=6419085","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,7,21]],"date-time":"2020-07-21T13:10:51Z","timestamp":1595337051000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6419085\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,12]]},"references-count":27,"URL":"https:\/\/doi.org\/10.1109\/apccas.2012.6419085","relation":{},"subject":[],"published":{"date-parts":[[2012,12]]}}}