{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T03:54:47Z","timestamp":1725508487063},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,12]]},"DOI":"10.1109\/apccas.2012.6419110","type":"proceedings-article","created":{"date-parts":[[2013,1,30]],"date-time":"2013-01-30T17:53:42Z","timestamp":1359568422000},"page":"615-618","source":"Crossref","is-referenced-by-count":0,"title":["Utilizing register transfer level false paths for circuit optimization with a logic synthesis tool"],"prefix":"10.1109","author":[{"given":"Tsuyoshi","family":"Iwagaki","sequence":"first","affiliation":[]},{"given":"Takehiro","family":"Mikami","sequence":"additional","affiliation":[]},{"given":"Hideyuki","family":"Ichihara","sequence":"additional","affiliation":[]},{"given":"Tomoo","family":"Inoue","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/43.31522"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.1986.1270207"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.885737"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2011.5937850"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/ICVD.1997.567965"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/43.511566"},{"journal-title":"Synthesis and Optimization of Digital Circuit","year":"1994","author":"micheli","key":"1"},{"key":"10","doi-asserted-by":"crossref","first-page":"423","DOI":"10.1109\/ICVD.2005.99","article-title":"False path and clock scheduling based yield-aware gate sizing","author":"tsai","year":"2005","journal-title":"Proc of VLSI Design"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1991.185197"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/ICVD.1996.489643"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/EURDAC.1996.558208"},{"key":"4","first-page":"233","article-title":"An efficient method to identify untestable path delay faults","author":"reddy","year":"2001","journal-title":"Proc 10th Asian Test Symp"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/DTIS.2010.5487557"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2009.4796555"}],"event":{"name":"APCCAS 2012-2012 IEEE Asia Pacific Conference on Circuits and Systems","start":{"date-parts":[[2012,12,2]]},"location":"Kaohsiung, Taiwan","end":{"date-parts":[[2012,12,5]]}},"container-title":["2012 IEEE Asia Pacific Conference on Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6412846\/6418954\/06419110.pdf?arnumber=6419110","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,21]],"date-time":"2017-06-21T02:42:50Z","timestamp":1498012970000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6419110\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,12]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/apccas.2012.6419110","relation":{},"subject":[],"published":{"date-parts":[[2012,12]]}}}