{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,3]],"date-time":"2024-09-03T18:06:16Z","timestamp":1725386776130},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,11]]},"DOI":"10.1109\/apccas.2014.7032704","type":"proceedings-article","created":{"date-parts":[[2015,2,11]],"date-time":"2015-02-11T17:20:39Z","timestamp":1423675239000},"page":"1-4","source":"Crossref","is-referenced-by-count":1,"title":["High performance adaptive routing for Network-on-Chip systems with express highway mechanism"],"prefix":"10.1109","author":[{"given":"Shih-Chieh","family":"Lin","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"En-Jui","family":"Chang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yu-Yin","family":"Chen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hsien-Kai","family":"Hsin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"An-Yeu Andy","family":"Wu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/PDCAT.2010.42"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1006\/jpdc.2002.1837"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2011.01.003"},{"journal-title":"Network-on-Chip simulator","article-title":"Noxim","year":"2008","key":"ref13"},{"article-title":"Principles and Practices of Interconnection Networks","year":"2004","author":"dally","key":"ref14"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2010.26"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.4378787"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/160985.161018"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/71.877831"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2008.38"},{"article-title":"Interconnection Networks: An Engineering Approach","year":"2002","author":"duato","key":"ref7"},{"key":"ref2","doi-asserted-by":"crossref","first-page":"408","DOI":"10.1145\/1080695.1070004","article-title":"Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling","author":"kumar","year":"2005","journal-title":"IEEE International Symposium on Computer Architecture"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/2.976921"},{"key":"ref9","first-page":"203","article-title":"Regional Congestion Awareness for Load Balance in Network-on-Chip","author":"gratz","year":"2008","journal-title":"IEEE International Symposium on High-Performance Computer Architecture"}],"event":{"name":"2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","start":{"date-parts":[[2014,11,17]]},"location":"Ishigaki, Japan","end":{"date-parts":[[2014,11,20]]}},"container-title":["2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7021138\/7032694\/07032704.pdf?arnumber=7032704","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,23]],"date-time":"2017-06-23T01:21:58Z","timestamp":1498180918000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7032704\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,11]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/apccas.2014.7032704","relation":{},"subject":[],"published":{"date-parts":[[2014,11]]}}}