{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T10:21:56Z","timestamp":1729678916813,"version":"3.28.0"},"reference-count":8,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,11]]},"DOI":"10.1109\/apccas.2014.7032721","type":"proceedings-article","created":{"date-parts":[[2015,2,11]],"date-time":"2015-02-11T17:20:39Z","timestamp":1423675239000},"page":"69-72","source":"Crossref","is-referenced-by-count":2,"title":["A unified flagged prefix constant addition-subtraction scheme for design of area and power efficient binary floating-point and constant integer arithmetic circuits"],"prefix":"10.1109","author":[{"given":"Soumya","family":"Ganguly","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Abhishek","family":"Mittal","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Syed Ershad","family":"Ahmed","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.B.","family":"Srinivas","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2010.03.001"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1023\/A:1015421507166"},{"article-title":"Shared hardware for multiply, divide, and square root exponent calculation","year":"1997","author":"robert","key":"ref6"},{"key":"ref5","first-page":"1","article-title":"A Reconfigurable Parallel Prefix Ling Adder with modified Enhanced Flagged Binary logic","author":"soumya","year":"2012","journal-title":"2012 Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics PRIMEASIA"},{"year":"2002","key":"ref8","article-title":"Israel Koren, in: Computer Arithmetic Algorithms"},{"article-title":"Binary Adder Architectures for Cell-Based VLSI and their synthesis","year":"1997","author":"zimmermann","key":"ref7"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1117\/12.325715"},{"key":"ref1","doi-asserted-by":"crossref","first-page":"225","DOI":"10.4236\/cs.2011.23032","article-title":"Fast Signed-Digit Multi-operand Decimal Adders","volume":"2","author":"jeff","year":"2011","journal-title":"Circuits and Systems"}],"event":{"name":"2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","start":{"date-parts":[[2014,11,17]]},"location":"Ishigaki, Japan","end":{"date-parts":[[2014,11,20]]}},"container-title":["2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7021138\/7032694\/07032721.pdf?arnumber=7032721","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,23]],"date-time":"2017-06-23T01:21:56Z","timestamp":1498180916000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7032721\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,11]]},"references-count":8,"URL":"https:\/\/doi.org\/10.1109\/apccas.2014.7032721","relation":{},"subject":[],"published":{"date-parts":[[2014,11]]}}}