{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T09:41:42Z","timestamp":1729676502482,"version":"3.28.0"},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,10]]},"DOI":"10.1109\/apccas.2016.7803915","type":"proceedings-article","created":{"date-parts":[[2017,1,11]],"date-time":"2017-01-11T16:22:50Z","timestamp":1484151770000},"page":"135-138","source":"Crossref","is-referenced-by-count":2,"title":["Lateral silicon nanowire based standard cell design for higher performance"],"prefix":"10.1109","author":[{"given":"Om.","family":"Prakash","sequence":"first","affiliation":[]},{"given":"M.","family":"Sharma","sequence":"additional","affiliation":[]},{"given":"A.","family":"Bulusu","sequence":"additional","affiliation":[]},{"given":"A. K.","family":"Saxena","sequence":"additional","affiliation":[]},{"given":"S. K.","family":"Manhas","sequence":"additional","affiliation":[]},{"given":"S.","family":"Maheshwaram","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1007\/s10825-013-0449-8"},{"key":"ref11","doi-asserted-by":"crossref","first-page":"3379","DOI":"10.1109\/TED.2011.2162521","article-title":"Predictive 3-D modeling of parasitic gate capacitance in gate-all-around cylindrical silicon nanowire MOSFETs","volume":"58","author":"zou","year":"2011","journal-title":"IEEE Trans Electron Devices"},{"key":"ref12","first-page":"424","article-title":"5nm FinFET standard cell library optimization and circuit synthesis in near-and super-threshold voltage regimes","author":"xie","year":"2014","journal-title":"Proc IEEE Comput Soc Annu Symp VLSI ISVLSI"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2015.2391632"},{"year":"0","key":"ref14","article-title":"16nm PTM-MG"},{"key":"ref4","first-page":"2008","article-title":"Sub-10 nm gate-all-around CMOS nanowire transistors on bulk Si substrate","author":"li","year":"2009","journal-title":"2009 Symp VLSI Technol"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1021\/nl025875l"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2006.890264"},{"key":"ref5","first-page":"1","article-title":"High Performance 5nm radius Twin Silicon Nanowire MOSFET (TSNWFET): Fabrication on Bulk Si Wafer, Characteristics, and Reliability","volume":"0","author":"suk","year":"2005","journal-title":"Int Electron Devices Meet Tech Dig"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/T-ED.1983.21207"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2008.2005184"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1016\/j.mee.2007.04.038"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2004.833965"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1016\/j.sse.2011.09.001"}],"event":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","start":{"date-parts":[[2016,10,25]]},"location":"Jeju, South Korea","end":{"date-parts":[[2016,10,28]]}},"container-title":["2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7786273\/7803879\/07803915.pdf?arnumber=7803915","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,25]],"date-time":"2017-06-25T04:00:12Z","timestamp":1498363212000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7803915\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,10]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/apccas.2016.7803915","relation":{},"subject":[],"published":{"date-parts":[[2016,10]]}}}