{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,9]],"date-time":"2025-11-09T03:38:57Z","timestamp":1762659537783,"version":"3.44.0"},"reference-count":9,"publisher":"IEEE","license":[{"start":{"date-parts":[[2016,10,1]],"date-time":"2016-10-01T00:00:00Z","timestamp":1475280000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2016,10,1]],"date-time":"2016-10-01T00:00:00Z","timestamp":1475280000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,10]]},"DOI":"10.1109\/apccas.2016.7803985","type":"proceedings-article","created":{"date-parts":[[2017,1,11]],"date-time":"2017-01-11T16:22:50Z","timestamp":1484151770000},"page":"396-399","source":"Crossref","is-referenced-by-count":4,"title":["ASIC design of a low-complexity K-best Viterbi decoder for IoT applications"],"prefix":"10.1109","author":[{"given":"Hiromasa","family":"Kato","sequence":"first","affiliation":[{"name":"Graduation School of Information Science, Nara Institute of Science and Technology, Takayama 8916-5, Ikoma, Nara, Japan"}]},{"given":"Thi Hong","family":"Tran","sequence":"additional","affiliation":[{"name":"Graduation School of Information Science, Nara Institute of Science and Technology, Takayama 8916-5, Ikoma, Nara, Japan"}]},{"given":"Yasuhiko","family":"Nakashima","sequence":"additional","affiliation":[{"name":"Graduation School of Information Science, Nara Institute of Science and Technology, Takayama 8916-5, Ikoma, Nara, Japan"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2006.124"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2012.42"},{"key":"ref6","first-page":"42","article-title":"Implementation of convolution encoder and viterbi decoder for constraint length 7 and bit rate 1\/2","volume":"3","author":"rambabu","year":"2013","journal-title":"International Journal of Engineering Reasearch and Application"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCOM.1984.1096023"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/DDECS.2013.6549790"},{"key":"ref7","article-title":"ASIC implementation of soft decision viterbi decoder for GSM application","volume":"70","author":"chaitanyat","year":"2007","journal-title":"SASTECH Journal MSRSAS 6 65"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1186\/1687-1499-2014-93"},{"key":"ref9","article-title":"Design of a low power viterbi decoder for wireless communication applications","author":"chih-jhen chen","year":"2010","journal-title":"2010 IEEE 14th InternationalSymposium on Consumer Electronics IEEE"},{"key":"ref1","article-title":"IEEE 802.11–11\/1137r15","author":"park","year":"2013","journal-title":"Intel Hillsboro USA"}],"event":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","start":{"date-parts":[[2016,10,25]]},"location":"Jeju, Korea (South)","end":{"date-parts":[[2016,10,28]]}},"container-title":["2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7786273\/7803879\/07803985.pdf?arnumber=7803985","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,14]],"date-time":"2025-08-14T18:41:09Z","timestamp":1755196869000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/7803985\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,10]]},"references-count":9,"URL":"https:\/\/doi.org\/10.1109\/apccas.2016.7803985","relation":{},"subject":[],"published":{"date-parts":[[2016,10]]}}}