{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T16:53:55Z","timestamp":1729616035333,"version":"3.28.0"},"reference-count":11,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,10]]},"DOI":"10.1109\/apccas.2016.7804014","type":"proceedings-article","created":{"date-parts":[[2017,1,11]],"date-time":"2017-01-11T16:22:50Z","timestamp":1484151770000},"page":"502-505","source":"Crossref","is-referenced-by-count":2,"title":["Simultaneous layer-aware and region-aware partitioning for 3D IC"],"prefix":"10.1109","author":[{"given":"Yung-Hao","family":"Lai","sequence":"first","affiliation":[]},{"given":"Yang Lang","family":"Chang","sequence":"additional","affiliation":[]},{"given":"Jyh-Perng","family":"Fang","sequence":"additional","affiliation":[]},{"given":"Jie","family":"Lee","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/1412587.1412592"},{"journal-title":"Handbook of 3D Integration","year":"2008","author":"philip","key":"ref3"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/1127908.1127928"},{"key":"ref6","first-page":"31","article-title":"Early stage power management for 3D FPGAs considering hierarchical routing resources","author":"chaitanya","year":"2013","journal-title":"ACM Great Lakes Symposium on VLSI 2013"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1002\/9783527623051"},{"key":"ref5","doi-asserted-by":"crossref","first-page":"228","DOI":"10.1109\/TCAD.2011.2174640","article-title":"Assembling 2-D Blocks into 3-D Chips","volume":"31","author":"johann","year":"2012","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"ref8","first-page":"176","article-title":"Parallel Layer-Aware Partitioning for 3D Designs","author":"chen","year":"2013","journal-title":"SASIMI The 18th Workshop on Synthesis And System Integration of Mixed Information Technologies"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2011.16"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1147\/rd.504.0491"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2011.16"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/5.929647"}],"event":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","start":{"date-parts":[[2016,10,25]]},"location":"Jeju, South Korea","end":{"date-parts":[[2016,10,28]]}},"container-title":["2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7786273\/7803879\/07804014.pdf?arnumber=7804014","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,25]],"date-time":"2017-06-25T04:00:10Z","timestamp":1498363210000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7804014\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,10]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/apccas.2016.7804014","relation":{},"subject":[],"published":{"date-parts":[[2016,10]]}}}