{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,5]],"date-time":"2025-11-05T06:33:31Z","timestamp":1762324411735},"reference-count":16,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,10]]},"DOI":"10.1109\/apccas.2018.8605602","type":"proceedings-article","created":{"date-parts":[[2019,1,23]],"date-time":"2019-01-23T22:28:04Z","timestamp":1548282484000},"page":"115-118","source":"Crossref","is-referenced-by-count":3,"title":["Type-4 2-D Diagonal and Four-Fold Rotational Symmetry Digital Filter Architectures"],"prefix":"10.1109","author":[{"given":"Lan-Da","family":"Van","sequence":"first","affiliation":[]},{"given":"Tsung-Che","family":"Lu","sequence":"additional","affiliation":[]},{"given":"Pei-Yu","family":"Chen","sequence":"additional","affiliation":[]},{"given":"Hari C.","family":"Reddy","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"ref10","DOI":"10.1109\/ISCAS.2009.5117693"},{"doi-asserted-by":"publisher","key":"ref11","DOI":"10.1109\/TCSI.2010.2055274"},{"doi-asserted-by":"publisher","key":"ref12","DOI":"10.1109\/ICICS.2013.6782888"},{"doi-asserted-by":"publisher","key":"ref13","DOI":"10.1007\/s11045-013-0232-9"},{"doi-asserted-by":"publisher","key":"ref14","DOI":"10.1109\/MWSCAS.2017.8052911"},{"doi-asserted-by":"publisher","key":"ref15","DOI":"10.1109\/ASICON.2017.8252578"},{"key":"ref16","article-title":"Symmetry incorporated cost-effective architectures for two-dimensional digital filters","author":"van","year":"0","journal-title":"IEEE Circuits and Systems Magazine"},{"year":"1995","author":"sid-ahmed","journal-title":"Image Processing Theory Algorithms and Architectures","key":"ref4"},{"year":"1992","author":"lu","journal-title":"Two-Dimensional Digital Filters","key":"ref3"},{"doi-asserted-by":"publisher","key":"ref6","DOI":"10.1109\/78.80972"},{"doi-asserted-by":"publisher","key":"ref5","DOI":"10.1109\/MCAS.2012.2237141"},{"doi-asserted-by":"publisher","key":"ref8","DOI":"10.1109\/MCAS.2003.1263396"},{"doi-asserted-by":"publisher","key":"ref7","DOI":"10.1109\/TVLSI.2002.800531"},{"year":"1989","author":"oppenheim","journal-title":"Discrete-Time Signal Processing","key":"ref2"},{"year":"1984","author":"dudgeon","journal-title":"Multidimensional Digital Signal Processing","key":"ref1"},{"key":"ref9","first-page":"320","article-title":"A new VLSI 2-D diagonal-symmetry filter architecture design","author":"chen","year":"2008","journal-title":"Proc IEEE APCCAS"}],"event":{"name":"2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","start":{"date-parts":[[2018,10,26]]},"location":"Chengdu","end":{"date-parts":[[2018,10,30]]}},"container-title":["2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8596720\/8605562\/08605602.pdf?arnumber=8605602","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,8,23]],"date-time":"2020-08-23T22:16:13Z","timestamp":1598220973000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8605602\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,10]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/apccas.2018.8605602","relation":{},"subject":[],"published":{"date-parts":[[2018,10]]}}}