{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,15]],"date-time":"2024-09-15T14:32:29Z","timestamp":1726410749523},"reference-count":17,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,10]]},"DOI":"10.1109\/apccas.2018.8605632","type":"proceedings-article","created":{"date-parts":[[2019,1,24]],"date-time":"2019-01-24T03:28:04Z","timestamp":1548300484000},"page":"257-260","source":"Crossref","is-referenced-by-count":1,"title":["Analytical Modeling of Process Variability in Subthreshold Regime for Ultra Low Power Applications"],"prefix":"10.1109","author":[{"given":"Anala","family":"M.","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"B.P.","family":"Harish","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2009.2039529"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2012.2184377"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/NEWCAS.2010.5603925"},{"key":"ref13","article-title":"Analytical delay and variations modeling in the subthreshold region","author":"kim","year":"2016","journal-title":"Proceedings of the National Conference on Undergraduate Research (NCUR)"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2011.2158704"},{"journal-title":"Fundamentals of Modern VLSI Devices","year":"1998","author":"taur","key":"ref15"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1016\/j.sse.2006.07.005"},{"journal-title":"Predictive Technology Model","year":"0","key":"ref17"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/LPE.2005.195479"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1166\/jolpe.2008.177"},{"key":"ref6","article-title":"Verification of the alpha-power law by a CMOS inverter chain","author":"kim","year":"2016","journal-title":"B S Thesis Report"},{"key":"ref5","first-page":"98","article-title":"Models of process variations in device and interconnect","author":"boning","year":"2000","journal-title":"Design of High Performance Microprocessor Circuits IEEE Press"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.827602"},{"key":"ref7","first-page":"61","article-title":"Robust analytical gate delay modeling for low voltage circuits","author":"ramalingam","year":"2006","journal-title":"Asia and South Pacific Conference on Design Automation"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.883910"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/4.982424"},{"key":"ref9","article-title":"Complete delay modeling of sub-threshold CMOS logic gates for low-power application","author":"chanda","year":"2015","journal-title":"Int J Numer Modeling Electron Networks"}],"event":{"name":"2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","start":{"date-parts":[[2018,10,26]]},"location":"Chengdu, China","end":{"date-parts":[[2018,10,30]]}},"container-title":["2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8596720\/8605562\/08605632.pdf?arnumber=8605632","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,27]],"date-time":"2022-01-27T23:04:52Z","timestamp":1643324692000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8605632\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,10]]},"references-count":17,"URL":"https:\/\/doi.org\/10.1109\/apccas.2018.8605632","relation":{},"subject":[],"published":{"date-parts":[[2018,10]]}}}