{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,8]],"date-time":"2024-09-08T11:44:20Z","timestamp":1725795860297},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,10]]},"DOI":"10.1109\/apccas.2018.8605678","type":"proceedings-article","created":{"date-parts":[[2019,1,23]],"date-time":"2019-01-23T22:28:04Z","timestamp":1548282484000},"page":"279-282","source":"Crossref","is-referenced-by-count":4,"title":["40-nm 2\u00d7VDD Digital Output Buffer Design With DDR4-Compliant Slew Rate"],"prefix":"10.1109","author":[{"given":"Chua-Chin","family":"Wang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zong-You","family":"Hou","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ssu-Wei","family":"Huang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","first-page":"1","article-title":"On-chip MOS PVT variation monitor for slew rate self-adjusting 2×VDD output buffers","author":"chen","year":"2012","journal-title":"Int Conf on IC Design and Technology (ICICDT)"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2013.2244351"},{"key":"ref12","first-page":"2079","article-title":"A high-speed 2×VDD output buffer with PVT detection using 40-nm CMOS technology","author":"wang","year":"2013","journal-title":"Proc IEEE Int Symp On Circuits and Systems (ISCAS)"},{"key":"ref13","first-page":"1","article-title":"Slew rate improved 2×VDD output buffer using leakage and delay compensation","author":"lee","year":"2014","journal-title":"Proc IEEE Int Conf on Electron Devices and Solid-State Circuits (EDSSC)"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2016.7527311"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2014.6865462"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.843599"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/4.910493"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2013.2244351"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2012.2215744"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2007.373467"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2014.09.010"},{"key":"ref2","first-page":"97","article-title":"Design of 2.5 V\/5 V mixed-voltage CMOS I\/O buffer with only thin oxide device and dynamic N-well bias circuit","author":"ker","year":"2003","journal-title":"Proc IEEE Int Symp On Circuits and Systems (ISCAS)"},{"key":"ref1","first-page":"23.3.1","article-title":"3.3V-5V compatible I\/O circuit without thick gate oxide","author":"takahashi","year":"1992","journal-title":"Proc IEEE Custom Integrated Circuits Conf"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2009.2038631"}],"event":{"name":"2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","start":{"date-parts":[[2018,10,26]]},"location":"Chengdu","end":{"date-parts":[[2018,10,30]]}},"container-title":["2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8596720\/8605562\/08605678.pdf?arnumber=8605678","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,8,24]],"date-time":"2020-08-24T02:09:40Z","timestamp":1598234980000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8605678\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,10]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/apccas.2018.8605678","relation":{},"subject":[],"published":{"date-parts":[[2018,10]]}}}