{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T08:39:14Z","timestamp":1725698354865},"reference-count":11,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,11,1]],"date-time":"2019-11-01T00:00:00Z","timestamp":1572566400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,11,1]],"date-time":"2019-11-01T00:00:00Z","timestamp":1572566400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,11,1]],"date-time":"2019-11-01T00:00:00Z","timestamp":1572566400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,11]]},"DOI":"10.1109\/apccas47518.2019.8953158","type":"proceedings-article","created":{"date-parts":[[2020,1,9]],"date-time":"2020-01-09T20:40:02Z","timestamp":1578602402000},"page":"229-232","source":"Crossref","is-referenced-by-count":6,"title":["A 0.14-to-0.29-pJ\/bit 14-GBaud\/s Trimodal (NRZ\/PAM-4\/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery Circuit (BBCDR) in 28-nm CMOS"],"prefix":"10.1109","author":[{"given":"Xiaoteng","family":"Zhao","sequence":"first","affiliation":[]},{"given":"Yong","family":"Chen","sequence":"additional","affiliation":[]},{"given":"Pui-In","family":"Mak","sequence":"additional","affiliation":[]},{"given":"Rui P.","family":"Martins","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"ref4","DOI":"10.1109\/JSSC.2013.2237692"},{"doi-asserted-by":"publisher","key":"ref3","DOI":"10.1109\/ASSCC.2018.8579307"},{"key":"ref10","first-page":"1","article-title":"Comparator with built-in reference voltage generation and split-ROM encoder for a highspeed flash ADC","author":"chen","year":"2015","journal-title":"ISSCS 2015"},{"doi-asserted-by":"publisher","key":"ref6","DOI":"10.1109\/ASSCC.2016.7844141"},{"doi-asserted-by":"publisher","key":"ref11","DOI":"10.1109\/TVLSI.2019.2915769"},{"doi-asserted-by":"publisher","key":"ref5","DOI":"10.1109\/ASSCC.2014.7008917"},{"doi-asserted-by":"publisher","key":"ref8","DOI":"10.1049\/el:19750415"},{"key":"ref7","first-page":"271","article-title":"A 14 µm × 26 µm 20-Gb\/s 3-mW CDR circuit with high jitter tolerance","author":"kong","year":"2018","journal-title":"VLSI 2018"},{"doi-asserted-by":"publisher","key":"ref2","DOI":"10.1109\/ASSCC.2017.8240223"},{"doi-asserted-by":"publisher","key":"ref9","DOI":"10.1109\/ICSICT.2012.6467783"},{"doi-asserted-by":"publisher","key":"ref1","DOI":"10.1109\/JSSC.2015.2433269"}],"event":{"name":"2019 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","start":{"date-parts":[[2019,11,11]]},"location":"Bangkok, Thailand","end":{"date-parts":[[2019,11,14]]}},"container-title":["2019 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8944232\/8953069\/08953158.pdf?arnumber=8953158","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,17]],"date-time":"2022-07-17T17:49:23Z","timestamp":1658080163000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8953158\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,11]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/apccas47518.2019.8953158","relation":{},"subject":[],"published":{"date-parts":[[2019,11]]}}}