{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,18]],"date-time":"2025-11-18T09:30:35Z","timestamp":1763458235401,"version":"3.37.3"},"reference-count":16,"publisher":"IEEE","license":[{"start":{"date-parts":[[2022,11,11]],"date-time":"2022-11-11T00:00:00Z","timestamp":1668124800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,11,11]],"date-time":"2022-11-11T00:00:00Z","timestamp":1668124800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100012166","name":"National Key R&D Program and NSFC of China","doi-asserted-by":"publisher","award":["2018YFB2202900,61904197,61934005"],"award-info":[{"award-number":["2018YFB2202900,61904197,61934005"]}],"id":[{"id":"10.13039\/501100012166","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2022,11,11]]},"DOI":"10.1109\/apccas55924.2022.10090254","type":"proceedings-article","created":{"date-parts":[[2023,4,11]],"date-time":"2023-04-11T17:25:39Z","timestamp":1681233939000},"page":"497-500","source":"Crossref","is-referenced-by-count":1,"title":["RRAM Computing-in-Memory Using Transient Charge Transferring for Low-Power and Small-Latency AI Edge Inference"],"prefix":"10.1109","author":[{"given":"Linfang","family":"Wang","sequence":"first","affiliation":[{"name":"Institute of Microelectronics of Chinese Academy of Sciences"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Junjie","family":"An","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of Chinese Academy of Sciences"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wang","family":"Ye","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of Chinese Academy of Sciences"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Weizeng","family":"Li","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of Chinese Academy of Sciences"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hanghang","family":"Gao","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of Chinese Academy of Sciences"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yangu","family":"He","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of Chinese Academy of Sciences"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jianfeng","family":"Gao","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of Chinese Academy of Sciences"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jinshan","family":"Yue","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of Chinese Academy of Sciences"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lingyan","family":"Fan","sequence":"additional","affiliation":[{"name":"Hangzhou Dianzi University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chunmeng","family":"Dou","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of Chinese Academy of Sciences"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2018.8510627"},{"key":"ref2","first-page":"577","article-title":"Fully hardware-implemented memristor convolutional neural network","author":"Peng","year":"2020","journal-title":"Nature"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1038\/s41928-020-0435-7"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM19574.2021.9720546"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1038\/s41928-019-0288-0"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1038\/s41928-021-00676-9"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2021.3067385"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/VLSITechnology18217.2020.9265066"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9062995"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9062985"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42613.2021.9365984"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/CICC51472.2021.9431398"},{"key":"ref13","first-page":"1","article-title":"Fully Row\/Column-Parallel In-memory Computing SRAM Macro employing Capacitor-based Mixed-signal Computation with 5-b Inputs","volume-title":"2021 Symposium on VLSI Technology","author":"Lee","year":"2021"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42613.2021.9365926"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42614.2022.9731725"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2880918"}],"event":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","start":{"date-parts":[[2022,11,11]]},"location":"Shenzhen, China","end":{"date-parts":[[2022,11,13]]}},"container-title":["2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10090225\/10090247\/10090254.pdf?arnumber=10090254","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,3,3]],"date-time":"2024-03-03T11:29:13Z","timestamp":1709465353000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10090254\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,11,11]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/apccas55924.2022.10090254","relation":{},"subject":[],"published":{"date-parts":[[2022,11,11]]}}}