{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,20]],"date-time":"2026-02-20T07:18:31Z","timestamp":1771571911637,"version":"3.50.1"},"reference-count":10,"publisher":"IEEE","license":[{"start":{"date-parts":[[2025,10,12]],"date-time":"2025-10-12T00:00:00Z","timestamp":1760227200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,10,12]],"date-time":"2025-10-12T00:00:00Z","timestamp":1760227200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025,10,12]]},"DOI":"10.1109\/apccas67402.2025.11377200","type":"proceedings-article","created":{"date-parts":[[2026,2,19]],"date-time":"2026-02-19T20:54:40Z","timestamp":1771534480000},"page":"1-5","source":"Crossref","is-referenced-by-count":0,"title":["A 99.1 dB-SNDR CT-DT NS SAR ADC with Two-Stage Stacking Inverter-Cascoded FIA"],"prefix":"10.1109","author":[{"given":"Yanzhujun","family":"Du","sequence":"first","affiliation":[{"name":"Institute of VLSI, Zhejiang University,Hangzhou,China,310063"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lingxin","family":"Meng","sequence":"additional","affiliation":[{"name":"Institute of VLSI, Zhejiang University,Hangzhou,China,310063"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Menglian","family":"Zhao","sequence":"additional","affiliation":[{"name":"Institute of VLSI, Zhejiang University,Hangzhou,China,310063"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zhichao","family":"Tan","sequence":"additional","affiliation":[{"name":"Institute of VLSI, Zhejiang University,Hangzhou,China,310063"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2019.8662406"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/CICC60959.2024.10528994"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.3020194"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2022.3171790"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS46773.2023.10181887"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2957193"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42613.2021.9366002"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2024.3488364"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/iscas58744.2024.10558527"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2786724"}],"event":{"name":"2025 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","location":"Busan, Korea, Republic of","start":{"date-parts":[[2025,10,12]]},"end":{"date-parts":[[2025,10,15]]}},"container-title":["2025 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11373921\/11376610\/11377200.pdf?arnumber=11377200","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,2,20]],"date-time":"2026-02-20T06:57:40Z","timestamp":1771570660000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11377200\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,10,12]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/apccas67402.2025.11377200","relation":{},"subject":[],"published":{"date-parts":[[2025,10,12]]}}}