{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T07:10:38Z","timestamp":1725433838182},"reference-count":16,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2008,8]]},"DOI":"10.1109\/apcsac.2008.4625446","type":"proceedings-article","created":{"date-parts":[[2008,9,18]],"date-time":"2008-09-18T18:03:25Z","timestamp":1221761005000},"page":"1-8","source":"Crossref","is-referenced-by-count":0,"title":["Mechanism for return stack and branch history corrections under misprediction in deep pipeline design"],"prefix":"10.1109","author":[{"family":"Guan-Ying Chiu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Hui-Chin Yang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Walter Yuan-Hwa","family":"Li","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Chung-Ping Chung","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/2.869367"},{"key":"16","article-title":"cacti 3.0: an integrated cache timing, power, and area model","author":"shivakumar","year":"0","journal-title":"WRL Research Report"},{"article-title":"intel corporation. return address predictor that uses branch instructions to track a last valid return address. united state","year":"2001","author":"yeh","key":"13"},{"key":"14","article-title":"correct alignment of a return-address-stack after call and return mispredictions","author":"desmet","year":"2005","journal-title":"4th WDDD (ISCA-32)"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1998.742787"},{"year":"0","key":"12"},{"year":"0","key":"3"},{"article-title":"international business machines corporation. computer system branch prediction of subroutine returns. united state","year":"1994","author":"eickemeyer","key":"2"},{"article-title":"evaluating future microprocessors: the simplescalar tool set","year":"1996","author":"burger","key":"1"},{"year":"0","key":"10"},{"year":"0","key":"7"},{"journal-title":"Checkpoint repair for high-performance out-of-order execution machines IEEE Transactions on Computers","year":"1987","author":"hwu","key":"6"},{"article-title":"intel corporation. return register stack target predictor. united state","year":"2003","author":"hummel","key":"5"},{"article-title":"intel corporation. method and apparatus for implementing a four stage branch resolution system in a computer processor","year":"0","author":"hoyt","key":"4"},{"article-title":"ip-first, llc. method and apparatus for correcting an internal call\/return stack in a microprocessor that speculatively executes call and return instrcutions. united state","year":"2001","author":"mcdonald","key":"9"},{"year":"0","key":"8"}],"event":{"name":"2008 13th Asia-Pacific Computer Systems Architecture Conference (ACSAC)","start":{"date-parts":[[2008,8,4]]},"location":"Hsinchu","end":{"date-parts":[[2008,8,6]]}},"container-title":["2008 13th Asia-Pacific Computer Systems Architecture Conference"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4610266\/4625425\/04625446.pdf?arnumber=4625446","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,17]],"date-time":"2017-03-17T15:59:18Z","timestamp":1489766358000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4625446\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,8]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/apcsac.2008.4625446","relation":{},"subject":[],"published":{"date-parts":[[2008,8]]}}}