{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,19]],"date-time":"2025-03-19T14:22:27Z","timestamp":1742394147065,"version":"3.28.0"},"reference-count":13,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/arith.2003.1207655","type":"proceedings-article","created":{"date-parts":[[2004,2,3]],"date-time":"2004-02-03T19:24:01Z","timestamp":1075836241000},"page":"12-19","source":"Crossref","is-referenced-by-count":20,"title":["Multiple-precision fixed-point vector multiply-accumulator using shared segmentation"],"prefix":"10.1109","author":[{"given":"D.","family":"Tan","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A.","family":"Danysh","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"Liebelt","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","article-title":"A High-Performance and Low-Power 32-bit Multiply-Accumulate Unit with Single-Instruction-Multiple-Data (SIMD) Feature","volume":"37","author":"liao","year":"2002","journal-title":"IEEE J of Solid-State Cir"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/SIPS.1997.625683"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS.1998.814842"},{"key":"ref13","first-page":"325","article-title":"Trading bitwidth for array size: a unified reconfigurable arithmetic processor design","author":"lin","year":"2001","journal-title":"Int Symp Quality Electronic Design"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/PGEC.1964.263830"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/12.102823"},{"key":"ref6","first-page":"178-180","article-title":"Computer Arithmetic - Algorithms and Hardware Designs","author":"parhami","year":"2000"},{"key":"ref5","first-page":"349","article-title":"Some Schemes For Parallel Multipliers","volume":"34","author":"dadda","year":"1965","journal-title":"Alta Freq"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1998.706891"},{"key":"ref7","article-title":"A Low-power, High-speed Implementation of a PowerPC™ Microprocessor Vector Extension","author":"schmookler","year":"1999","journal-title":"Comp Arith 1999 Proc 14th IEEE Symp"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1093\/qjmam\/4.2.236"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1998.742766"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1049\/el:19921119"}],"event":{"name":"16th IEEE Symposium on Computer Arithmetic","acronym":"ARITH-03","location":"Santiago de Compostela, Spain"},"container-title":["16th IEEE Symposium on Computer Arithmetic, 2003. Proceedings."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8582\/27181\/01207655.pdf?arnumber=1207655","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,13]],"date-time":"2017-03-13T19:21:32Z","timestamp":1489432892000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1207655\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/arith.2003.1207655","relation":{},"subject":[]}}