{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,4]],"date-time":"2026-06-04T03:19:44Z","timestamp":1780543184399,"version":"3.54.1"},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,6]]},"DOI":"10.1109\/arith.2018.8464695","type":"proceedings-article","created":{"date-parts":[[2018,9,17]],"date-time":"2018-09-17T22:06:04Z","timestamp":1537221964000},"page":"5-12","source":"Crossref","is-referenced-by-count":23,"title":["High Density and Performance Multiplication for FPGA"],"prefix":"10.1109","author":[{"given":"Martin","family":"Langhammer","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Gregg","family":"Baeckler","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ARITH.2015.17"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1973.223648"},{"key":"ref12","doi-asserted-by":"crossref","first-page":"236","DOI":"10.1093\/qjmam\/4.2.236","article-title":"A signed binary multiplication technique","volume":"4","author":"booth","year":"1951","journal-title":"The Quarterly Journal of Mechanics and Applied Mathematics"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JRPROC.1961.287779"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ACSSC.2014.7094659"},{"key":"ref15","doi-asserted-by":"crossref","DOI":"10.3390\/computers5040020","article-title":"Array multipliers for high throughput in xilinx FPGAs with 6-input LUTs","volume":"5","author":"walters","year":"2016","journal-title":"Computers"},{"key":"ref4","year":"2017","journal-title":"Microsoft unveils project brainwave for real-time ai"},{"key":"ref3","doi-asserted-by":"crossref","first-page":"117","DOI":"10.1145\/2684746.2689071","article-title":"Floating-point DSP block architecture for FPGAs","author":"langhammer","year":"2015","journal-title":"Proceedings of the 2015 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays ser FPGA '15"},{"key":"ref6","year":"2014","journal-title":"Arria10 Device Overview"},{"key":"ref5","year":"2017","journal-title":"UltraScale Architecture-DSP Slice User Guide"},{"key":"ref8","year":"2015","journal-title":"Cyclone V Device Handbook"},{"key":"ref7","year":"2016","journal-title":"7 Series DSP48El Slice User Guide"},{"key":"ref2","year":"2018"},{"key":"ref1","year":"0","journal-title":"Intel Stratix 10 High-Performance Design Handbook 2017"},{"key":"ref9","year":"2017","journal-title":"Deep learning with INT8 optimization on Xilinx devices"}],"event":{"name":"2018 IEEE 25th Symposium on Computer Arithmetic (ARITH)","location":"Amherst, MA","start":{"date-parts":[[2018,6,25]]},"end":{"date-parts":[[2018,6,27]]}},"container-title":["2018 IEEE 25th Symposium on Computer Arithmetic (ARITH)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8452530\/8464686\/08464695.pdf?arnumber=8464695","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,7,7]],"date-time":"2025-07-07T17:14:22Z","timestamp":1751908462000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8464695\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,6]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/arith.2018.8464695","relation":{},"subject":[],"published":{"date-parts":[[2018,6]]}}}