{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,4,5]],"date-time":"2025-04-05T10:24:30Z","timestamp":1743848670161},"reference-count":9,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/asap.2002.1030715","type":"proceedings-article","created":{"date-parts":[[2003,6,25]],"date-time":"2003-06-25T22:14:31Z","timestamp":1056579271000},"page":"151-162","source":"Crossref","is-referenced-by-count":3,"title":["A mathematical model of trace cache"],"prefix":"10.1109","author":[{"given":"A.","family":"Hossain","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"D.J.","family":"Pease","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J.S.","family":"Burns","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"N.","family":"Parveen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"journal-title":"The SimpleScalar Web Site","year":"0","key":"ref4"},{"key":"ref3","article-title":"The SimpleScalar Tool Set","author":"doug","year":"1997","journal-title":"Version 2 0 University of Wisconsin-Madison Computer Science Department Technical Report #1342"},{"article-title":"Trace Cache Design for Wide-issue Superscalar Processors","year":"1999","author":"patel","key":"ref6"},{"journal-title":"Standard Performance Evaluation Corporation","year":"0","key":"ref5"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/232973.232993"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1997.645793"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/71.689444"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/12.48865"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/12.752652"}],"event":{"name":"IEEE International Conference on Application- Specific Systems, Architectures, and Processors","acronym":"ASAP-02","location":"San Jose, CA, USA"},"container-title":["Proceedings IEEE International Conference on Application- Specific Systems, Architectures, and Processors"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8009\/22137\/01030715.pdf?arnumber=1030715","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,10]],"date-time":"2017-03-10T16:25:17Z","timestamp":1489163117000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1030715\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":9,"URL":"https:\/\/doi.org\/10.1109\/asap.2002.1030715","relation":{},"subject":[]}}