{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,8]],"date-time":"2024-09-08T04:34:22Z","timestamp":1725770062812},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2007,7]]},"DOI":"10.1109\/asap.2007.4429953","type":"proceedings-article","created":{"date-parts":[[2008,1,14]],"date-time":"2008-01-14T20:09:20Z","timestamp":1200341360000},"page":"24-29","source":"Crossref","is-referenced-by-count":6,"title":["A Self-Reconfigurable Implementation of the JPEG Encoder"],"prefix":"10.1109","author":[{"given":"Antonino","family":"Tumeo","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Matteo","family":"Monchiero","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Gianluca","family":"Palermo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Fabrizio","family":"Ferrandi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Donatella","family":"Sciuto","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","first-page":"211","article-title":"Modular partial reconfigurable in Virtex FPGAs","author":"sedcole","year":"2005","journal-title":"FPL'05 International Conference on Field Programmable Logic and Applications"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/1176254.1176307"},{"key":"ref12","article-title":"Improving instruction level parallelism through reconfigurable units in superscalar processors","author":"suri","year":"2006","journal-title":"RAAW'06 Reconfigurable and Adaptive Architecture Workshop"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2007.13"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2003.1193225"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2004.104"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2005.25"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/508352.508353"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2006.67"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1997.624608"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.1996.542825"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2006.311188"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1997.624606"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2006.886411"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2006.62"}],"event":{"name":"2007 IEEE International Conf. on Application-specific Systems, Architectures and Processors","start":{"date-parts":[[2007,7,9]]},"location":"Montreal, QC, Canada","end":{"date-parts":[[2007,7,11]]}},"container-title":["2007 IEEE International Conf. on Application-specific Systems, Architectures and Processors (ASAP)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4429947\/4429948\/04429953.pdf?arnumber=4429953","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,16]],"date-time":"2017-03-16T20:00:32Z","timestamp":1489694432000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4429953\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,7]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/asap.2007.4429953","relation":{},"subject":[],"published":{"date-parts":[[2007,7]]}}}