{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T10:45:49Z","timestamp":1730198749613,"version":"3.28.0"},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2007,7]]},"DOI":"10.1109\/asap.2007.4429997","type":"proceedings-article","created":{"date-parts":[[2008,3,17]],"date-time":"2008-03-17T17:40:06Z","timestamp":1205775606000},"page":"302-307","source":"Crossref","is-referenced-by-count":12,"title":["Latency Reduction of Global Traffic in Wormhole-Routed Meshes Using Hierarchical Rings for Global Routing"],"prefix":"10.1109","author":[{"given":"S.","family":"Bourduas","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Z.","family":"Zilic","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"crossref","first-page":"1025","DOI":"10.1109\/TC.2005.134","article-title":"Performance evaluation and design trade-offs for Network-on-Chip interconnect architectures","volume":"54","author":"grecu","year":"2005","journal-title":"IEEE Trans Comput"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ICPP.2000.876165"},{"key":"ref12","doi-asserted-by":"crossref","DOI":"10.1109\/DATE.2000.840047","article-title":"A generic architecture for on-chip packet switched interconnections","author":"guerrier","year":"2000"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.1997.569606"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/12.859540"},{"key":"ref15","doi-asserted-by":"crossref","first-page":"81","DOI":"10.1016\/j.sysarc.2003.07.005","article-title":"Packetization and routing analysis of on-chip multiprocessor networks","volume":"50","author":"ye","year":"2004","journal-title":"Journal of Systems Architecture"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/NEWCAS.2006.250914"},{"key":"ref3","article-title":"A RTL-Ievel analysis of a hierarchical ring interconnect for Network-on-Chip multi-processors","author":"bourduas","year":"2006","journal-title":"Proc International SoC Design Conference (ISOCC)"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ASIC.2002.1158058"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2007.3"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/378239.379048"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/12.83652"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/2.976921"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1049\/PBCS018E_ch17"},{"key":"ref9","article-title":"Evaluation of routing algorithms on mesh based NoCs","author":"de mello","year":"2004","journal-title":"Faculdade de Informatica Pucrs - Brazil Tech Rep"}],"event":{"name":"IEEE 18th International Conference Application-specific Systems, Architectures and Processors","start":{"date-parts":[[2007,7,9]]},"location":"Montreal, Que.","end":{"date-parts":[[2007,7,11]]}},"container-title":["2007 IEEE International Conf. on Application-specific Systems, Architectures and Processors (ASAP)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4429947\/4429948\/04429997.pdf?arnumber=4429997","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2018,12,7]],"date-time":"2018-12-07T00:52:32Z","timestamp":1544143952000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/4429997\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,7]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/asap.2007.4429997","relation":{},"subject":[],"published":{"date-parts":[[2007,7]]}}}