{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,8]],"date-time":"2024-09-08T14:23:45Z","timestamp":1725805425097},"reference-count":16,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2008,7]]},"DOI":"10.1109\/asap.2008.4580177","type":"proceedings-article","created":{"date-parts":[[2008,8,4]],"date-time":"2008-08-04T15:35:12Z","timestamp":1217864112000},"page":"191-196","source":"Crossref","is-referenced-by-count":23,"title":["Accelerating Nussinov RNA secondary structure prediction with systolic arrays on FPGAs"],"prefix":"10.1109","author":[{"given":"Arpith","family":"Jacob","sequence":"first","affiliation":[]},{"given":"Jeremy","family":"Buhler","sequence":"additional","affiliation":[]},{"given":"Roger D.","family":"Chamberlain","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"15","article-title":"an experimental study of optimizing bioinformatics applications","author":"tan","year":"2006","journal-title":"Proc Int Symp Parallel Distrib Process"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1016\/0076-6879(89)80106-5"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1007\/BF01558666"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1093\/nar\/22.23.5112"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1137\/0135006"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1007\/BF02944781"},{"key":"3","first-page":"25","article-title":"synthesizing systolic arrays using diastol","author":"gachet","year":"1986","journal-title":"International Workshop on Systolic Arrays"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1146\/annurev.biophys.30.1.457"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1016\/j.sbi.2006.05.001"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1101\/gr.6836108"},{"key":"7","doi-asserted-by":"crossref","DOI":"10.1201\/9781482276046-23","article-title":"advanced systolic design","author":"lavenier","year":"1999","journal-title":"Digital Signal Processing for Multimedia Systems"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/CSB.2003.1227315"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1038\/418244a"},{"key":"4","first-page":"509","article-title":"direct vlsi implementation of combinatorial algorithms","author":"guibas","year":"1979","journal-title":"Cal Tech Conf VLSI"},{"key":"9","first-page":"63130","author":"moscola","year":"2008","journal-title":"Techniques for hardware-accelerated parsing for network and bioinformatic applications"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1986.1676652"}],"event":{"name":"2008 International Conference on Application-Specific Systems, Architectures and Processors (ASAP)","start":{"date-parts":[[2008,7,2]]},"location":"Leuven, Belgium","end":{"date-parts":[[2008,7,4]]}},"container-title":["2008 International Conference on Application-Specific Systems, Architectures and Processors"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4569858\/4580144\/04580177.pdf?arnumber=4580177","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,13]],"date-time":"2019-05-13T03:41:11Z","timestamp":1557718871000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4580177\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,7]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/asap.2008.4580177","relation":{},"subject":[],"published":{"date-parts":[[2008,7]]}}}