{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T10:46:14Z","timestamp":1730198774133,"version":"3.28.0"},"reference-count":16,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,7]]},"DOI":"10.1109\/asap.2010.5540760","type":"proceedings-article","created":{"date-parts":[[2010,8,10]],"date-time":"2010-08-10T11:51:40Z","timestamp":1281441100000},"page":"125-132","source":"Crossref","is-referenced-by-count":1,"title":["Modeling and synthesis of communication subsystems for loop accelerator pipelines"],"prefix":"10.1109","author":[{"given":"Hritam","family":"Dutta","sequence":"first","affiliation":[{"name":"University ofErlangen-Nuremberg, Germany"}]},{"given":"Frank","family":"Hannig","sequence":"additional","affiliation":[{"name":"University ofErlangen-Nuremberg, Germany"}]},{"given":"Moritz","family":"Schmid","sequence":"additional","affiliation":[{"name":"University ofErlangen-Nuremberg, Germany"}]},{"given":"Joachim","family":"Keinert","sequence":"additional","affiliation":[{"name":"Fraunhofer Institute for Integrated Circuits, Germany"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/78.485935"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TSP.2002.800830"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISPAN.2005.70"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2006.7"},{"key":"ref14","doi-asserted-by":"crossref","first-page":"73","DOI":"10.1007\/s11265-006-0045-2","article-title":"Master Interface for On-Chip Hardware Accelerator Burst Communications","volume":"49","author":"fraboulet","year":"2007","journal-title":"J of VLSI Signal Processing Systems"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/1016720.1016730"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2002.1030701"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-78153-0_11"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-78610-8_30"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/334012.334015"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4757-4903-8"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1007\/s10766-006-0011-4"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1007\/BF00925828"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/43.739055"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP.2006.1660798"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1987.5009446"}],"event":{"name":"2010 21st IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)","start":{"date-parts":[[2010,7,7]]},"location":"Rennes, France","end":{"date-parts":[[2010,7,9]]}},"container-title":["ASAP 2010 - 21st IEEE International Conference on Application-specific Systems, Architectures and Processors"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5523683\/5540749\/05540760.pdf?arnumber=5540760","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,6,7]],"date-time":"2021-06-07T19:59:12Z","timestamp":1623095952000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/5540760\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,7]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/asap.2010.5540760","relation":{},"subject":[],"published":{"date-parts":[[2010,7]]}}}