{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T17:38:19Z","timestamp":1729618699509,"version":"3.28.0"},"reference-count":26,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,7]]},"DOI":"10.1109\/asap.2010.5540994","type":"proceedings-article","created":{"date-parts":[[2010,8,10]],"date-time":"2010-08-10T11:51:40Z","timestamp":1281441100000},"page":"175-182","source":"Crossref","is-referenced-by-count":1,"title":["Completeness of automatically generated instruction selectors"],"prefix":"10.1109","author":[{"given":"Florian","family":"Brandner","sequence":"first","affiliation":[]}],"member":"263","reference":[{"year":"2007","author":"comon","article-title":"Tree automata techniques and applications","key":"ref10"},{"year":"2009","author":"brandner","article-title":"Compiler backend generation from structural processor models","key":"ref11"},{"doi-asserted-by":"publisher","key":"ref12","DOI":"10.1145\/321958.321970"},{"doi-asserted-by":"publisher","key":"ref13","DOI":"10.1145\/322290.322295"},{"doi-asserted-by":"publisher","key":"ref14","DOI":"10.1145\/69558.75700"},{"key":"ref15","doi-asserted-by":"crossref","first-page":"49","DOI":"10.1007\/978-3-540-39920-9_5","article-title":"Code instruction selection based on SSA-graphs","volume":"2826 2003","author":"eckstein","year":"2003","journal-title":"LNCS-Software and Compilers for Embedded Systems"},{"doi-asserted-by":"publisher","key":"ref16","DOI":"10.1145\/277650.277752"},{"key":"ref17","doi-asserted-by":"crossref","first-page":"151","DOI":"10.1007\/BFb0054170","article-title":"Translation validation","author":"pnueli","year":"1998","journal-title":"TACAS '98 Proceedings of the 4th International Conference on Tools and Algorithms for Construction and Analysis of Systems"},{"doi-asserted-by":"publisher","key":"ref18","DOI":"10.1007\/11925040_6"},{"doi-asserted-by":"publisher","key":"ref19","DOI":"10.1007\/3-540-44518-8_11"},{"doi-asserted-by":"publisher","key":"ref4","DOI":"10.1109\/EDTC.1997.582348"},{"doi-asserted-by":"publisher","key":"ref3","DOI":"10.1145\/73141.74838"},{"doi-asserted-by":"publisher","key":"ref6","DOI":"10.1145\/1134650.1134671"},{"doi-asserted-by":"publisher","key":"ref5","DOI":"10.1145\/307418.307549"},{"year":"2009","author":"hohenauer","journal-title":"C Compilers for ASIPs Automatic Compiler Generation with LISA","key":"ref8"},{"doi-asserted-by":"publisher","key":"ref7","DOI":"10.1145\/1289881.1289886"},{"doi-asserted-by":"publisher","key":"ref2","DOI":"10.1145\/151640.151642"},{"key":"ref1","doi-asserted-by":"crossref","first-page":"68","DOI":"10.1145\/131080.131089","article-title":"BURG: Fast optimal instruction selection and tree parsing","volume":"27","author":"fraser","year":"1992","journal-title":"ACM SIGPLAN Notices"},{"doi-asserted-by":"publisher","key":"ref9","DOI":"10.1007\/3-540-55984-1_16"},{"doi-asserted-by":"publisher","key":"ref20","DOI":"10.1145\/1111037.1111042"},{"doi-asserted-by":"publisher","key":"ref22","DOI":"10.1016\/0304-3975(90)90145-8"},{"doi-asserted-by":"publisher","key":"ref21","DOI":"10.1007\/3-540-19027-9_17"},{"doi-asserted-by":"publisher","key":"ref24","DOI":"10.1145\/1543820.1543833"},{"year":"2008","author":"buchwald","article-title":"Befehlsauswahl auf expliziten Abhängigkeitsgraphen","key":"ref23"},{"doi-asserted-by":"publisher","key":"ref26","DOI":"10.1109\/EMRTS.2003.1212740"},{"key":"ref25","article-title":"Automatic tool generation from structural processor descriptions","author":"brandner","year":"2009","journal-title":"KPS '09 Proceedings of the 15th Biennial Workshop on Programmiersprachen und Grundlagen der Programmierung"}],"event":{"name":"2010 21st IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)","start":{"date-parts":[[2010,7,7]]},"location":"Rennes, France","end":{"date-parts":[[2010,7,9]]}},"container-title":["ASAP 2010 - 21st IEEE International Conference on Application-specific Systems, Architectures and Processors"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5523683\/5540749\/05540994.pdf?arnumber=5540994","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,6,1]],"date-time":"2019-06-01T11:04:22Z","timestamp":1559387062000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5540994\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,7]]},"references-count":26,"URL":"https:\/\/doi.org\/10.1109\/asap.2010.5540994","relation":{},"subject":[],"published":{"date-parts":[[2010,7]]}}}