{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T07:36:02Z","timestamp":1729668962701,"version":"3.28.0"},"reference-count":32,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,6]]},"DOI":"10.1109\/asap.2013.6567565","type":"proceedings-article","created":{"date-parts":[[2013,8,1]],"date-time":"2013-08-01T20:13:23Z","timestamp":1375388003000},"page":"125-132","source":"Crossref","is-referenced-by-count":2,"title":["A compact and scalable RNS architecture"],"prefix":"10.1109","author":[{"given":"Pedro Miguens","family":"Matutino","sequence":"first","affiliation":[]},{"given":"Ricardo","family":"Chaves","sequence":"additional","affiliation":[]},{"given":"Leonel","family":"Sousa","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS.2009.5410923"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2003.821516"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2007.895515"},{"key":"15","doi-asserted-by":"crossref","first-page":"399","DOI":"10.1049\/ip-cdt:20050166","article-title":"efficient new approach for modulo 2\/sup n\/-1 addition in rns","volume":"153","author":"patel","year":"2006","journal-title":"IEE Proceedings - Computers and Digital Techniques"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/TSP.2002.1011216"},{"key":"13","doi-asserted-by":"crossref","first-page":"210","DOI":"10.1109\/DSD.2004.1333279","article-title":"2n + 1, 2n+k, 2n 1: A new RNS moduli set extension","author":"chaves","year":"2004","journal-title":"EUROMICRO Systems on Digital System Design"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1049\/el:20056837"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/78.747787"},{"key":"12","first-page":"188","article-title":"Reverse converters for the moduli sets {22N ? 1, 2N, 22N +1} and {2N ?3, 2N +1, 2N ?1, 2N +3}","author":"ananda mohan","year":"2004","journal-title":"SPCOM '04"},{"key":"21","first-page":"1","article-title":"RNS reverse converters for moduli sets with dynamic ranges up to (8n+1)-bit","volume":"pp","author":"pettenghi","year":"2012","journal-title":"IEEE Trans on Circuits and Systems"},{"key":"20","doi-asserted-by":"crossref","first-page":"158","DOI":"10.1109\/ARITH.1999.762841","article-title":"Efficient VLSI implementation of modulo {2n \ufffd1} addition and multiplication","author":"zimmermann","year":"1999","journal-title":"14th IEEE Symposium on Computer Arithmetic"},{"key":"22","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2012.114"},{"key":"23","first-page":"460","article-title":"Binary-to-RNS conversion units for moduli {2n\ufffd3}","author":"matutino","year":"2011","journal-title":"Proc 10th EUROMICRO Conf Digital System Design Architectures Methods and Tools"},{"key":"24","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2010.77"},{"key":"25","doi-asserted-by":"publisher","DOI":"10.1109\/12.250610"},{"key":"26","doi-asserted-by":"publisher","DOI":"10.1049\/el:19960026"},{"key":"27","doi-asserted-by":"crossref","DOI":"10.1142\/p523","author":"omondi","year":"2007","journal-title":"Residue Number Systems Theory and Implementation"},{"key":"28","doi-asserted-by":"publisher","DOI":"10.1109\/82.826745"},{"key":"29","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2012.2188456"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/82.404073"},{"key":"2","first-page":"2451","author":"barraclough","year":"1989","journal-title":"The Design and Implementation of the IMS A110 Image and Signal Processor"},{"key":"10","first-page":"165","author":"skavantzos","year":"1999","journal-title":"Application of New Chinese Remainder Theorems to RNS with Two Pairs of Conjugate Moduli"},{"journal-title":"Residue Arithmetic and its Applications to Computer Technology","year":"1967","author":"szabo","key":"1"},{"key":"30","first-page":"694","article-title":"Efficient modulo 2n + 1 multi-operand adders","author":"vergos","year":"2008","journal-title":"Electronics Circuits and Systems 2008 ICECS 2008"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2008.107"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/82.331549"},{"journal-title":"90 Nm Technology Standard Cell Library","year":"2006","key":"32"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1147\/rd.353.0367"},{"key":"31","doi-asserted-by":"crossref","first-page":"241","DOI":"10.1007\/BF00929618","article-title":"An efficient tree architecture for modulo 2n+1 multiplication","volume":"14","author":"wang","year":"1996","journal-title":"J VLSI Signal Process Syst"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/12.381948"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/82.559370"},{"key":"8","first-page":"7","article-title":"Video coding with H.264\/AVC: Tools, performance, and complexity","year":"2004","journal-title":"IEEE Circuits and Systems Magazine"}],"event":{"name":"2013 IEEE 24th International Conference on Application-specific Systems, Architectures and Processors (ASAP)","start":{"date-parts":[[2013,6,5]]},"location":"Washington, DC, USA","end":{"date-parts":[[2013,6,7]]}},"container-title":["2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6558539\/6567524\/06567565.pdf?arnumber=6567565","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,7,20]],"date-time":"2019-07-20T06:39:11Z","timestamp":1563604751000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6567565\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,6]]},"references-count":32,"URL":"https:\/\/doi.org\/10.1109\/asap.2013.6567565","relation":{},"subject":[],"published":{"date-parts":[[2013,6]]}}}