{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,28]],"date-time":"2025-08-28T00:06:36Z","timestamp":1756339596650,"version":"3.44.0"},"reference-count":5,"publisher":"IEEE","license":[{"start":{"date-parts":[[2011,10,1]],"date-time":"2011-10-01T00:00:00Z","timestamp":1317427200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2011,10,1]],"date-time":"2011-10-01T00:00:00Z","timestamp":1317427200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,10]]},"DOI":"10.1109\/asicon.2011.6157183","type":"proceedings-article","created":{"date-parts":[[2012,2,28]],"date-time":"2012-02-28T15:44:14Z","timestamp":1330443854000},"page":"307-310","source":"Crossref","is-referenced-by-count":0,"title":["Word line boost and read SA PMOS compensation (SAPC) for ROM in 55nm CMOS"],"prefix":"10.1109","author":[{"family":"Ruifeng Huang","sequence":"first","affiliation":[{"name":"Aicestar Technology Corp., Suzhou, China"}]},{"family":"Jianbin Zheng","sequence":"additional","affiliation":[{"name":"Aicestar Technology Corp., Suzhou, China"}]},{"family":"Lijun Zhang","sequence":"additional","affiliation":[{"name":"School of Urban Rail Transportation, Soochow University, Suzhou, China"}]},{"family":"Zhaoyong Zhang","sequence":"additional","affiliation":[{"name":"Aicestar Technology Corp., Suzhou, China"}]},{"family":"Hao Wu","sequence":"additional","affiliation":[{"name":"Aicestar Technology Corp., Suzhou, China"}]},{"family":"Yue Yu","sequence":"additional","affiliation":[{"name":"Aicestar Technology Corp., Suzhou, China"}]}],"member":"263","reference":[{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2003.816138"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2002.808156"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2003.816145"},{"key":"5","article-title":"A Process-Variation-Tolerant Dual-Power-Supply SRAM with 0.179um2 Cell in 40nm CMOS Using Level-Programmable Wordline Drive","author":"hirabayashi","year":"2009","journal-title":"ISSCC2009"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2008.4672110"}],"event":{"name":"2011 IEEE 9th International Conference on ASIC (ASICON 2011)","start":{"date-parts":[[2011,10,25]]},"location":"Xiamen, China","end":{"date-parts":[[2011,10,28]]}},"container-title":["2011 9th IEEE International Conference on ASIC"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6153219\/6157041\/06157183.pdf?arnumber=6157183","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,27]],"date-time":"2025-08-27T18:27:58Z","timestamp":1756319278000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6157183\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,10]]},"references-count":5,"URL":"https:\/\/doi.org\/10.1109\/asicon.2011.6157183","relation":{},"subject":[],"published":{"date-parts":[[2011,10]]}}}