{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,1,2]],"date-time":"2025-01-02T05:25:33Z","timestamp":1735795533010,"version":"3.32.0"},"reference-count":8,"publisher":"IEEE","license":[{"start":{"date-parts":[[2013,10,1]],"date-time":"2013-10-01T00:00:00Z","timestamp":1380585600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2013,10,1]],"date-time":"2013-10-01T00:00:00Z","timestamp":1380585600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,10]]},"DOI":"10.1109\/asicon.2013.6811836","type":"proceedings-article","created":{"date-parts":[[2014,5,16]],"date-time":"2014-05-16T21:51:33Z","timestamp":1400277093000},"page":"1-4","source":"Crossref","is-referenced-by-count":0,"title":["MCVP-NoC: Many-Core Virtual Platform with Networks-on-Chip support"],"prefix":"10.1109","author":[{"family":"Dexue Zhang","sequence":"first","affiliation":[{"name":"State Key Lab. of ASIC & System, Fudan University, Shanghai 200240, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Xiaoyang Zeng","sequence":"additional","affiliation":[{"name":"State Key Lab. of ASIC & System, Fudan University, Shanghai 200240, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Zongyan Wang","sequence":"additional","affiliation":[{"name":"State Key Lab. of ASIC & System, Fudan University, Shanghai 200240, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Weike Wang","sequence":"additional","affiliation":[{"name":"College of Information Science and Engineering, Shandong University of Science and Technology, Qingdao 266590, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Xinhua Chen","sequence":"additional","affiliation":[{"name":"Qingdao ShanHai Microelectronics Co., Ltd., 266590, China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"year":"0","key":"3"},{"year":"0","key":"2"},{"key":"1","article-title":"Network on chip: An architecture for billion transistor era","author":"hemani","year":"2000","journal-title":"Proceeding of the IEEE NorChip Conference"},{"year":"0","key":"7"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2009.4919636"},{"year":"0","key":"5"},{"year":"0","key":"4"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2091686"}],"event":{"name":"2013 IEEE 10th International Conference on ASIC (ASICON 2013)","start":{"date-parts":[[2013,10,28]]},"location":"Shenzhen, China","end":{"date-parts":[[2013,10,31]]}},"container-title":["2013 IEEE 10th International Conference on ASIC"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6805351\/6811820\/06811836.pdf?arnumber=6811836","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,1]],"date-time":"2025-01-01T19:23:55Z","timestamp":1735759435000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6811836\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,10]]},"references-count":8,"URL":"https:\/\/doi.org\/10.1109\/asicon.2013.6811836","relation":{},"subject":[],"published":{"date-parts":[[2013,10]]}}}