{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T10:49:36Z","timestamp":1730198976761,"version":"3.28.0"},"reference-count":7,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,11]]},"DOI":"10.1109\/asicon.2015.7517211","type":"proceedings-article","created":{"date-parts":[[2016,7,26]],"date-time":"2016-07-26T20:38:31Z","timestamp":1469565511000},"page":"1-4","source":"Crossref","is-referenced-by-count":0,"title":["Study and implementation of cluster hierarchical memory system of multicore cryptographic processor"],"prefix":"10.1109","author":[{"given":"Junwei","family":"Li","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zibin","family":"Dai","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wei","family":"Li","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tao","family":"Chen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yufei","family":"Zhu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","first-page":"98","article-title":"Subtask-based data allocation mechanism of MCP","volume":"36","author":"dai","year":"2015","journal-title":"Computer Engineering and Design"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1016\/j.mee.2014.04.023"},{"journal-title":"Design and Implementation of Data-Parallel Memory System for Tiled Stream Processor","year":"2009","author":"wang","key":"ref6"},{"journal-title":"Research on Key Technology of Reconfigurable Manycore Stream Processor Architecture","year":"2012","author":"xu","key":"ref5"},{"key":"ref7","first-page":"287","article-title":"An efficient stream memory architecture for heterogeneous multicore processor","author":"deng","year":"0","journal-title":"IEEE Symposium on Computers and Communications 2009"},{"journal-title":"Study on Key Technology of Multi-core processors-Design and Implementation of Excute Array and Memory System","year":"2013","author":"zhang","key":"ref2"},{"key":"ref1","first-page":"113","article-title":"Research and Development of the Stream Processor Technology","volume":"4","author":"yang","year":"2008","journal-title":"Computer Engineering and Science"}],"event":{"name":"2015 IEEE 11th International Conference on ASIC (ASICON )","start":{"date-parts":[[2015,11,3]]},"location":"Chengdu, China","end":{"date-parts":[[2015,11,6]]}},"container-title":["2015 IEEE 11th International Conference on ASIC (ASICON)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7506193\/7516874\/07517211.pdf?arnumber=7517211","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,17]],"date-time":"2017-03-17T16:38:54Z","timestamp":1489768734000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7517211\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,11]]},"references-count":7,"URL":"https:\/\/doi.org\/10.1109\/asicon.2015.7517211","relation":{},"subject":[],"published":{"date-parts":[[2015,11]]}}}