{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T13:24:54Z","timestamp":1725715494702},"reference-count":7,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,10]]},"DOI":"10.1109\/asicon.2017.8252531","type":"proceedings-article","created":{"date-parts":[[2018,1,17]],"date-time":"2018-01-17T17:22:30Z","timestamp":1516209750000},"page":"537-540","source":"Crossref","is-referenced-by-count":7,"title":["Design of 56 Gb\/s PAM4 wire-line receiver with ring VCO based CDR in a 65 nm CMOS technology"],"prefix":"10.1109","author":[{"given":"Fangxu","family":"Lv","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jianye","family":"Wang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dengjie","family":"Wang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yongcong","family":"Liu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ziqiang","family":"Wang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2433269"},{"key":"ref3","first-page":"42","article-title":"60Gb\/s NRZ and PAM4 transmitters for 400GbE in 65nm CMOS","author":"chiang","year":"2014","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref6","article-title":"Design considerations for 2nd-order and 3rd-order bang-bang CDR loops","author":"wang","year":"2005","journal-title":"CICC Dig Tech Papers"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2009.2028449"},{"key":"ref7","first-page":"34","article-title":"Designing bang-bang PLLs for clock and data recovery in serial data transmission systems","author":"walker","year":"2003","journal-title":"Phase-Locking in High Performance Systems"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2411625"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2352299"}],"event":{"name":"2017 IEEE 12th International Conference on ASIC (ASICON)","start":{"date-parts":[[2017,10,25]]},"location":"Guiyang","end":{"date-parts":[[2017,10,28]]}},"container-title":["2017 IEEE 12th International Conference on ASIC (ASICON)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8240668\/8252386\/08252531.pdf?arnumber=8252531","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2018,2,15]],"date-time":"2018-02-15T10:56:39Z","timestamp":1518692199000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8252531\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,10]]},"references-count":7,"URL":"https:\/\/doi.org\/10.1109\/asicon.2017.8252531","relation":{},"subject":[],"published":{"date-parts":[[2017,10]]}}}