{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T10:50:09Z","timestamp":1730199009136,"version":"3.28.0"},"reference-count":11,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,10]]},"DOI":"10.1109\/asicon.2017.8252540","type":"proceedings-article","created":{"date-parts":[[2018,1,17]],"date-time":"2018-01-17T22:22:30Z","timestamp":1516227750000},"page":"573-576","source":"Crossref","is-referenced-by-count":1,"title":["Interface engineering of Si<inf>1\u2212x<\/inf>Ge<inf>x<\/inf> gate stacks for high performance dual channel CMOS"],"prefix":"10.1109","author":[{"given":"ChoongHyun","family":"Lee","sequence":"first","affiliation":[]},{"given":"Richard G.","family":"Southwick","sequence":"additional","affiliation":[]},{"given":"Shogo","family":"Mochizuki","sequence":"additional","affiliation":[]},{"given":"Paul","family":"Jamison","sequence":"additional","affiliation":[]},{"given":"Ruqiang","family":"Bao","sequence":"additional","affiliation":[]},{"given":"Rajan","family":"Pandey","sequence":"additional","affiliation":[]},{"given":"Aniruddha","family":"Konar","sequence":"additional","affiliation":[]},{"given":"Takashi","family":"Ando","sequence":"additional","affiliation":[]},{"given":"Vijay","family":"Narayanan","sequence":"additional","affiliation":[]},{"given":"Bala","family":"Haran","sequence":"additional","affiliation":[]},{"given":"Hemanth","family":"Jagannathan","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","volume":"36","author":"lee","year":"2016","journal-title":"VLSI"},{"key":"ref3","volume":"402","author":"hashemi","year":"2014","journal-title":"IEDM"},{"key":"ref10","first-page":"4587","volume":"90","author":"fischetti","year":"0","journal-title":"JAP"},{"key":"ref6","volume":"766","author":"lee","year":"2016","journal-title":"IEDM"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1103\/PhysRev.79.1013"},{"key":"ref5","volume":"38","author":"hashemi","year":"2016","journal-title":"VLSI"},{"key":"ref8","volume":"47","author":"lang","year":"1985","journal-title":"APL"},{"key":"ref7","volume":"149","author":"schaffler","year":"2001","journal-title":"Properties of Advanced Semiconductor Materials GaN AlN InN BN SiC SiGe"},{"key":"ref2","volume":"249","author":"mitard","year":"2010","journal-title":"IEDM"},{"key":"ref9","first-page":"2234","volume":"80","author":"fischetti","year":"1996","journal-title":"JAP"},{"key":"ref1","volume":"14","author":"guo","year":"2016","journal-title":"VLSI"}],"event":{"name":"2017 IEEE 12th International Conference on ASIC (ASICON)","start":{"date-parts":[[2017,10,25]]},"location":"Guiyang","end":{"date-parts":[[2017,10,28]]}},"container-title":["2017 IEEE 12th International Conference on ASIC (ASICON)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8240668\/8252386\/08252540.pdf?arnumber=8252540","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2018,2,22]],"date-time":"2018-02-22T21:30:12Z","timestamp":1519335012000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8252540\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,10]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/asicon.2017.8252540","relation":{},"subject":[],"published":{"date-parts":[[2017,10]]}}}