{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,21]],"date-time":"2025-08-21T18:02:51Z","timestamp":1755799371131,"version":"3.44.0"},"reference-count":10,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,10,1]],"date-time":"2019-10-01T00:00:00Z","timestamp":1569888000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,10,1]],"date-time":"2019-10-01T00:00:00Z","timestamp":1569888000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,10]]},"DOI":"10.1109\/asicon47005.2019.8983444","type":"proceedings-article","created":{"date-parts":[[2020,2,7]],"date-time":"2020-02-07T01:04:26Z","timestamp":1581037466000},"page":"1-4","source":"Crossref","is-referenced-by-count":0,"title":["Parallel Global Placement on CPU via Parallel Reduction"],"prefix":"10.1109","author":[{"given":"Huaidong","family":"Gao","sequence":"first","affiliation":[{"name":"State Key Lab of ASIC &#x0026; System, Fudan University,Shanghai,China,201203"}]},{"given":"Fan","family":"Yang","sequence":"additional","affiliation":[{"name":"State Key Lab of ASIC &#x0026; System, Fudan University,Shanghai,China,201203"}]},{"given":"Dian","family":"Zhou","sequence":"additional","affiliation":[{"name":"State Key Lab of ASIC &#x0026; System, Fudan University,Shanghai,China,201203"}]},{"given":"Xuan","family":"Zeng","sequence":"additional","affiliation":[{"name":"State Key Lab of ASIC &#x0026; System, Fudan University,Shanghai,China,201203"}]}],"member":"263","reference":[{"key":"ref4","article-title":"Parallel multi-level analytical global placement on graphics processing units","author":"jason","year":"0","journal-title":"Proceedings of the 2009 International Conference on Computer-Aided Design ACM"},{"key":"ref3","article-title":"VLSI placement and global routing using simulated annealing","volume":"54","author":"carl","year":"2012","journal-title":"Springer Science & Business Media"},{"key":"ref10","article-title":"Multilevel generalized force-directed method for circuit placement","author":"tony","year":"0","journal-title":"Proc 2005 ACM Int Symp Physical Design"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2003.159704"},{"key":"ref5","article-title":"Accelerate analytical placement with GPU: A generic approach","author":"chun-xun","year":"0","journal-title":"2018 Design Automation Test in Europe Conference Exhibition (DATE)"},{"key":"ref8","article-title":"NTUplace2: A hybrid placer using partitioning and analytical techniques","author":"zhe-wei","year":"0","journal-title":"Proceedings of the 2006 International Symposium on Physical Design ACM"},{"key":"ref7","article-title":"High-quality, deterministic parallel placement for FPGAs on commodity hardware","author":"adrian","year":"0","journal-title":"Proceedings of the 16th international ACM\/SIGDA symposium on Field programmable gate arrays ACM"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/1123008.1123057"},{"key":"ref9","article-title":"Non-linear optimization system and method for wire length and delay optimization for an automatic electric circuit placer","author":"naylor","year":"2001","journal-title":"U S Patent"},{"key":"ref1","article-title":"Improved cut sequences for partitioning based placement","author":"mehmet can","year":"0","journal-title":"Design Automation Conference 2001 Proceedings IEEE"}],"event":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","start":{"date-parts":[[2019,10,29]]},"location":"Chongqing, China","end":{"date-parts":[[2019,11,1]]}},"container-title":["2019 IEEE 13th International Conference on ASIC (ASICON)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8963812\/8983425\/08983444.pdf?arnumber=8983444","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,19]],"date-time":"2025-08-19T18:11:16Z","timestamp":1755627076000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8983444\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,10]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/asicon47005.2019.8983444","relation":{},"subject":[],"published":{"date-parts":[[2019,10]]}}}