{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,2]],"date-time":"2025-09-02T00:04:07Z","timestamp":1756771447775,"version":"3.44.0"},"reference-count":13,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,10,1]],"date-time":"2019-10-01T00:00:00Z","timestamp":1569888000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,10,1]],"date-time":"2019-10-01T00:00:00Z","timestamp":1569888000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,10]]},"DOI":"10.1109\/asicon47005.2019.8983483","type":"proceedings-article","created":{"date-parts":[[2020,2,7]],"date-time":"2020-02-07T01:04:26Z","timestamp":1581037466000},"page":"1-4","source":"Crossref","is-referenced-by-count":2,"title":["Buffer Sizing for Near-Threshold Clock Tree using Improved Genetic Algorithm"],"prefix":"10.1109","author":[{"given":"Yiran","family":"Sun","sequence":"first","affiliation":[{"name":"National ASIC System Engineering Research Center, School of Electronic Science & Engineering, Southeast University,Nanjing,China,210096"}]},{"given":"Ju","family":"Zhou","sequence":"additional","affiliation":[{"name":"College of Software Engineering (Suzhou), Southeast University,Suzhou,China,215123"}]},{"given":"Shiying","family":"Zhang","sequence":"additional","affiliation":[{"name":"College of Software Engineering (Suzhou), Southeast University,Suzhou,China,215123"}]},{"given":"Xuexiang","family":"Wang","sequence":"additional","affiliation":[{"name":"National ASIC System Engineering Research Center, School of Electronic Science & Engineering, Southeast University,Nanjing,China,210096"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2019088"},{"key":"ref11","volume":"2","author":"rabaey","year":"2002","journal-title":"Digital Integrated Circuits"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2014.6974686"},{"journal-title":"ISPD 2009 Clock Network Synthesis Contest ACM","year":"0","key":"ref13"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2144595"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2009.4810275"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.846362"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2016.2598581"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2013.10.008"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2013.2293067"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.1987.1270271"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/966747.966750"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1080\/1065514021000012200"}],"event":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","start":{"date-parts":[[2019,10,29]]},"location":"Chongqing, China","end":{"date-parts":[[2019,11,1]]}},"container-title":["2019 IEEE 13th International Conference on ASIC (ASICON)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8963812\/8983425\/08983483.pdf?arnumber=8983483","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,9,1]],"date-time":"2025-09-01T19:23:20Z","timestamp":1756754600000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8983483\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,10]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/asicon47005.2019.8983483","relation":{},"subject":[],"published":{"date-parts":[[2019,10]]}}}