{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,2]],"date-time":"2025-09-02T00:04:01Z","timestamp":1756771441757,"version":"3.44.0"},"reference-count":5,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,10,1]],"date-time":"2019-10-01T00:00:00Z","timestamp":1569888000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,10,1]],"date-time":"2019-10-01T00:00:00Z","timestamp":1569888000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,10]]},"DOI":"10.1109\/asicon47005.2019.8983576","type":"proceedings-article","created":{"date-parts":[[2020,2,7]],"date-time":"2020-02-07T01:04:26Z","timestamp":1581037466000},"page":"1-4","source":"Crossref","is-referenced-by-count":0,"title":["A Implementation for Built-in Self-Testing of RapidIO by JTAG"],"prefix":"10.1109","author":[{"given":"Hu","family":"Chunmei","sequence":"first","affiliation":[{"name":"School of Computer, National University of Defense Technology,Changsha,P.R. China,410073"}]},{"given":"Zhang","family":"Zhenyang","sequence":"additional","affiliation":[{"name":"School of Computer, National University of Defense Technology,Changsha,P.R. China,410073"}]},{"given":"Guo","family":"Yang","sequence":"additional","affiliation":[{"name":"School of Computer, National University of Defense Technology,Changsha,P.R. China,410073"}]},{"given":"Xu","family":"Jingyanan","sequence":"additional","affiliation":[{"name":"School of Computer, National University of Defense Technology,Changsha,P.R. China,410073"}]}],"member":"263","reference":[{"key":"ref4","first-page":"60","author":"xiaoxiao","year":"2013","journal-title":"SerDes circuit's testability integrated design and ATE testing (D)"},{"key":"ref3","article-title":"RapidIO Test Ideas and Methods (J)","author":"liangdeng","year":"2009","journal-title":"Electronic Quality Shangha"},{"key":"ref5","first-page":"103","author":"jianbo","year":"2013","journal-title":"Boundary Scan Testing Technology (A)"},{"key":"ref2","first-page":"88","article-title":"A RapidIO IP core design verification (J)","author":"yefang","year":"2014","journal-title":"Computer Technology and Development"},{"key":"ref1","first-page":"45","author":"tong","year":"2019","journal-title":"Key technology research on dual-channel serial RapidIO communication interface (D)"}],"event":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","start":{"date-parts":[[2019,10,29]]},"location":"Chongqing, China","end":{"date-parts":[[2019,11,1]]}},"container-title":["2019 IEEE 13th International Conference on ASIC (ASICON)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8963812\/8983425\/08983576.pdf?arnumber=8983576","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,9,1]],"date-time":"2025-09-01T19:23:12Z","timestamp":1756754592000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8983576\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,10]]},"references-count":5,"URL":"https:\/\/doi.org\/10.1109\/asicon47005.2019.8983576","relation":{},"subject":[],"published":{"date-parts":[[2019,10]]}}}