{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,2]],"date-time":"2025-09-02T00:03:55Z","timestamp":1756771435570,"version":"3.44.0"},"reference-count":9,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,10,1]],"date-time":"2019-10-01T00:00:00Z","timestamp":1569888000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,10,1]],"date-time":"2019-10-01T00:00:00Z","timestamp":1569888000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,10]]},"DOI":"10.1109\/asicon47005.2019.8983594","type":"proceedings-article","created":{"date-parts":[[2020,2,7]],"date-time":"2020-02-07T01:04:26Z","timestamp":1581037466000},"page":"1-4","source":"Crossref","is-referenced-by-count":1,"title":["A Polymorphic Circuit Interoperability Framework"],"prefix":"10.1109","author":[{"given":"Timothy","family":"Dunlap","sequence":"first","affiliation":[{"name":"University of Maryland,Department of Electrical and Computer Engineering and Institute for Systems Research,College Park,USA"}]},{"given":"Gang","family":"Qu","sequence":"additional","affiliation":[{"name":"University of Maryland,Department of Electrical and Computer Engineering and Institute for Systems Research,College Park,USA"}]},{"given":"Jinmei","family":"Lai","sequence":"additional","affiliation":[{"name":"State Key Library of ASIC and System Fudan University,Shanghai,China"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISMS.2016.62"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cdt:20040503"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/3194554.3194572"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2018.8297288"},{"key":"ref8","first-page":"7","article-title":"Implementing a unique chip ID on a reconfigurable polymorphic circuit","volume":"42 1","author":"lukas","year":"2013","journal-title":"information technology and control"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-45443-8_26"},{"key":"ref2","article-title":"On polymorphic circuits and their design using evolutionary algorithms","author":"stoica","year":"0","journal-title":"Proc of lASTED International Conference on Applied Informatics (AI2002)"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/2816818"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/UKSim.2015.82"}],"event":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","start":{"date-parts":[[2019,10,29]]},"location":"Chongqing, China","end":{"date-parts":[[2019,11,1]]}},"container-title":["2019 IEEE 13th International Conference on ASIC (ASICON)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8963812\/8983425\/08983594.pdf?arnumber=8983594","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,9,1]],"date-time":"2025-09-01T19:23:22Z","timestamp":1756754602000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8983594\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,10]]},"references-count":9,"URL":"https:\/\/doi.org\/10.1109\/asicon47005.2019.8983594","relation":{},"subject":[],"published":{"date-parts":[[2019,10]]}}}