{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,2]],"date-time":"2025-11-02T05:46:13Z","timestamp":1762062373622,"version":"3.37.3"},"reference-count":10,"publisher":"IEEE","license":[{"start":{"date-parts":[[2021,10,26]],"date-time":"2021-10-26T00:00:00Z","timestamp":1635206400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,10,26]],"date-time":"2021-10-26T00:00:00Z","timestamp":1635206400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,10,26]],"date-time":"2021-10-26T00:00:00Z","timestamp":1635206400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100006190","name":"Research and Development","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100006190","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,10,26]]},"DOI":"10.1109\/asicon52560.2021.9620360","type":"proceedings-article","created":{"date-parts":[[2021,12,1]],"date-time":"2021-12-01T20:53:36Z","timestamp":1638392016000},"page":"1-4","source":"Crossref","is-referenced-by-count":1,"title":["Design and Implementation of Full Adder in One-Transistor-One-Resistor RRAM Array"],"prefix":"10.1109","author":[{"given":"Xiangyu","family":"Zhang","sequence":"first","affiliation":[]},{"given":"Feng","family":"Wei","sequence":"additional","affiliation":[]},{"given":"Xiaoyan","family":"Liu","sequence":"additional","affiliation":[]},{"given":"Xiaole","family":"Cui","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2014.2357292"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1038\/nature08940"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2020.01.007"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2011.2127439"},{"key":"ref5","first-page":"1","author":"kvatinsky","year":"2012","journal-title":"2012 13th International Workshop on Cellular Nanoscale Networks and their Applications"},{"key":"ref8","first-page":"1","author":"huang","year":"2015","journal-title":"2015 IEEE International Memory Workshop (IMW2015)"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1002\/adma.201602418"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1088\/0268-1242\/31\/6\/063002"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2019.2931947"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2017.20"}],"event":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","start":{"date-parts":[[2021,10,26]]},"location":"Kunming, China","end":{"date-parts":[[2021,10,29]]}},"container-title":["2021 IEEE 14th International Conference on ASIC (ASICON)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9620208\/9620199\/09620360.pdf?arnumber=9620360","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T16:53:37Z","timestamp":1652201617000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9620360\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,10,26]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/asicon52560.2021.9620360","relation":{},"subject":[],"published":{"date-parts":[[2021,10,26]]}}}