{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,13]],"date-time":"2026-01-13T20:52:54Z","timestamp":1768337574578,"version":"3.49.0"},"reference-count":23,"publisher":"IEEE","license":[{"start":{"date-parts":[[2021,10,26]],"date-time":"2021-10-26T00:00:00Z","timestamp":1635206400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,10,26]],"date-time":"2021-10-26T00:00:00Z","timestamp":1635206400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,10,26]],"date-time":"2021-10-26T00:00:00Z","timestamp":1635206400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,10,26]]},"DOI":"10.1109\/asicon52560.2021.9620385","type":"proceedings-article","created":{"date-parts":[[2021,12,1]],"date-time":"2021-12-01T20:53:36Z","timestamp":1638392016000},"page":"1-4","source":"Crossref","is-referenced-by-count":5,"title":["Design of Analog CMOS-Memristive Neural Network Circuits for Pattern Recognition"],"prefix":"10.1109","author":[{"given":"Bo","family":"Li","sequence":"first","affiliation":[]},{"given":"Mingjie","family":"Yang","sequence":"additional","affiliation":[]},{"given":"Guoyong","family":"Shi","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TNNLS.2019.2899262"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/4.109558"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1146\/annurev.ne.18.030195.001351"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2136443"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2011.2180441"},{"key":"ref15","article-title":"A native SPICE implementation of memristor models for simulation of neuromorphic analog signal processing circuits","author":"li","year":"2021","journal-title":"ACM Transactions on Design Automation of Electronic Systems"},{"key":"ref16","article-title":"Memr-SPICE","author":"li","year":"2021"},{"key":"ref17","first-page":"315","article-title":"Deep sparse rectifier neural networks","author":"glorot","year":"0"},{"key":"ref18","first-page":"121","article-title":"CMOS implementation of rectfied linear activation function","author":"priyanka","year":"2018","journal-title":"Proc 22nd International Symposium on VLSI Design and Test"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1016\/j.neunet.2021.01.026"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2020.3013563"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1016\/j.neucom.2018.11.050"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/APCCAS47518.2019.8953177"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2016.7527510"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1063\/1.5143815"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2018.2871057"},{"key":"ref2","doi-asserted-by":"crossref","first-page":"1084","DOI":"10.1038\/s41586-020-1942-4","article-title":"Fully hardware-implemented memristor convolutional neural network","volume":"577","author":"yao","year":"2020","journal-title":"Nature"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1038\/nature06932"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2018.2866510"},{"key":"ref20","article-title":"Swish: a self-gated activation function","author":"ramachandran","year":"2017"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2109404"},{"key":"ref21","article-title":"Mish: A self regularized non-monotonic neural activation function","author":"misra","year":"2019"},{"key":"ref23","article-title":"scikit-learn Digit dataset","year":"0"}],"event":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","location":"Kunming, China","start":{"date-parts":[[2021,10,26]]},"end":{"date-parts":[[2021,10,29]]}},"container-title":["2021 IEEE 14th International Conference on ASIC (ASICON)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9620208\/9620199\/09620385.pdf?arnumber=9620385","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T16:53:39Z","timestamp":1652201619000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9620385\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,10,26]]},"references-count":23,"URL":"https:\/\/doi.org\/10.1109\/asicon52560.2021.9620385","relation":{},"subject":[],"published":{"date-parts":[[2021,10,26]]}}}