{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T00:58:14Z","timestamp":1725584294202},"reference-count":16,"publisher":"IEEE","license":[{"start":{"date-parts":[[2020,1,1]],"date-time":"2020-01-01T00:00:00Z","timestamp":1577836800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,1,1]],"date-time":"2020-01-01T00:00:00Z","timestamp":1577836800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,1,1]],"date-time":"2020-01-01T00:00:00Z","timestamp":1577836800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020,1]]},"DOI":"10.1109\/asp-dac47756.2020.9045102","type":"proceedings-article","created":{"date-parts":[[2020,3,27]],"date-time":"2020-03-27T12:27:10Z","timestamp":1585312030000},"page":"38-43","source":"Crossref","is-referenced-by-count":1,"title":["An Adaptive Electromigration Assessment Algorithm for Full-chip Power\/Ground Networks"],"prefix":"10.1109","author":[{"given":"Shaobin","family":"Ma","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xiaoyi","family":"Wang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sheldon X.-D.","family":"Tan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Liang","family":"Chen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jian","family":"He","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2018.2800707"},{"key":"ref11","first-page":"1","article-title":"Analytical modeling and characterization of electromigration effects for multi-branch interconnect trees","author":"chen","year":"2016","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"ref12","doi-asserted-by":"crossref","first-page":"1727","DOI":"10.23919\/DATE.2017.7927272","article-title":"Physical-based electromigration modeling and assessment for multi-segment interconnects in power grid networks","author":"wang","year":"2017","journal-title":"2017 Design Automation and Test in Europe"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2017.8203775"},{"key":"ref14","first-page":"1","article-title":"Fast analytic electromigration analysis for general multisegment interconnect wires","author":"chen","year":"2019","journal-title":"IEEE Trans Very Large Scale Integration Systems"},{"key":"ref15","first-page":"1","article-title":"Fast electromigration immortality analysis for multi-segment copper interconnect wires","author":"sun","year":"2018","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2008.4483978"},{"key":"ref4","first-page":"428","article-title":"IR-drop based electromigration assessment: Parametric failure chip-scale analysis","author":"sukharev","year":"2014","journal-title":"IEEE\/ACM International Conference on Computer-Aided Design"},{"key":"ref3","doi-asserted-by":"crossref","DOI":"10.1109\/TCAD.2016.2524540","article-title":"Physics-based electro-migration models and full-chip assessment for power grid networks","author":"huang","year":"2016","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-26172-6"},{"key":"ref5","first-page":"1","article-title":"Power grid electromigration checking using physics-based models","author":"chatterjee","year":"2017","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1063\/1.354073"},{"key":"ref7","first-page":"555","article-title":"Electromigration modeling and full-chip reliability analysis for BEOL interconnect in TSV-based 3D ICs","author":"pathak","year":"2011","journal-title":"IEEE\/ACM International Conference on Computer-Aided Design"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1063\/1.322842"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/SMACD.2016.7520752"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/T-ED.1969.16754"}],"event":{"name":"2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)","start":{"date-parts":[[2020,1,13]]},"location":"Beijing, China","end":{"date-parts":[[2020,1,16]]}},"container-title":["2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9036752\/9045099\/09045102.pdf?arnumber=9045102","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,6,27]],"date-time":"2022-06-27T15:45:24Z","timestamp":1656344724000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9045102\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,1]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/asp-dac47756.2020.9045102","relation":{},"subject":[],"published":{"date-parts":[[2020,1]]}}}