{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T00:57:58Z","timestamp":1725584278707},"reference-count":48,"publisher":"IEEE","license":[{"start":{"date-parts":[[2020,1,1]],"date-time":"2020-01-01T00:00:00Z","timestamp":1577836800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,1,1]],"date-time":"2020-01-01T00:00:00Z","timestamp":1577836800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,1,1]],"date-time":"2020-01-01T00:00:00Z","timestamp":1577836800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020,1]]},"DOI":"10.1109\/asp-dac47756.2020.9045352","type":"proceedings-article","created":{"date-parts":[[2020,3,27]],"date-time":"2020-03-27T12:27:10Z","timestamp":1585312030000},"page":"623-628","source":"Crossref","is-referenced-by-count":0,"title":["Timing Resilience for Efficient and Secure Circuits"],"prefix":"10.1109","author":[{"given":"Grace Li","family":"Zhang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michaela","family":"Brunner","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Bing","family":"Li","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Georg","family":"Sigl","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ulf","family":"Schlichtmann","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2013.6581566"},{"journal-title":"Split Manufacturing Method for Advanced Semiconductor Circuits","year":"2007","author":"jarvis","key":"ref38"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/IVSW.2017.8031550"},{"key":"ref32","article-title":"VirtualSync: Timing optimization by sychronizing logic waves with sequential and combinational components as delay units","author":"zhang","year":"2018","journal-title":"Proc Design Autom Conf"},{"key":"ref31","first-page":"100:1","article-title":"PieceTimer: A holistic timing analysis framework considering setup\/hold time interdependency using a piecewise model","author":"zhang","year":"2016","journal-title":"Proc Int Conf Comput -Aided Des"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2014.6783367"},{"journal-title":"Timing based camouflage circuit","year":"2019","author":"darmon","key":"ref37"},{"key":"ref36","doi-asserted-by":"crossref","first-page":"86","DOI":"10.46586\/tches.v2019.i3.86-118","article-title":"Covert gates: Protecting integrated circuits with undetectable camouflaging","author":"shakya","year":"2019","journal-title":"IACR Transactions on Cryptographic Hardware and Embedded Systems"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2028166"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1145\/1403375.1403631"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2432143"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1145\/3061639.3062226"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2015.0087"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.3850\/9783981537079_0250"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/SMACD.2018.8434898"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2898017"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/SOCC.2017.8226049"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2015.0087"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2009.56"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2013.12.002"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2898082"},{"key":"ref28","first-page":"96","author":"jain","year":"2005","journal-title":"Slack borrowing in flip-flop based sequential circuits"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/996566.996663"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2744812"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2007.907047"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2228305"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cds.2011.0347"},{"key":"ref5","first-page":"1320","article-title":"On hierarchical statistical static timing analysis","author":"li","year":"2009","journal-title":"Proc Design Automat Test Europe Conf"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2009.5355650"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253179"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2015.12.039"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2010.5653800"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488775"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2016.7495588"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS.2009.5195975"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1145\/3240765.3240857"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1997.643606"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2014.01.013"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2018.8624671"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2011.12.029"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/FDTC.2018.00010"},{"key":"ref24","first-page":"575","article-title":"Statistical timing analysis driven post-silicon-tunable clock-tree synthesis","author":"tsai","year":"2005","journal-title":"Proc Int Conf Comput -Aided Des"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2018.8351412"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2010.5654309"},{"key":"ref44","article-title":"TimingCamouflage: Improving circuit security against counterfeiting by unconventional timing","author":"zhang","year":"2018","journal-title":"Proc Design Automat Test Europe Conf"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2818713"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2762630"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2702632"}],"event":{"name":"2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)","start":{"date-parts":[[2020,1,13]]},"location":"Beijing, China","end":{"date-parts":[[2020,1,16]]}},"container-title":["2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9036752\/9045099\/09045352.pdf?arnumber=9045352","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,6,27]],"date-time":"2022-06-27T15:39:50Z","timestamp":1656344390000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9045352\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,1]]},"references-count":48,"URL":"https:\/\/doi.org\/10.1109\/asp-dac47756.2020.9045352","relation":{},"subject":[],"published":{"date-parts":[[2020,1]]}}}