{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,10]],"date-time":"2026-02-10T18:33:35Z","timestamp":1770748415438,"version":"3.50.0"},"reference-count":16,"publisher":"IEEE","license":[{"start":{"date-parts":[[2022,1,17]],"date-time":"2022-01-17T00:00:00Z","timestamp":1642377600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,1,17]],"date-time":"2022-01-17T00:00:00Z","timestamp":1642377600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2022,1,17]]},"DOI":"10.1109\/asp-dac52403.2022.9712485","type":"proceedings-article","created":{"date-parts":[[2022,2,21]],"date-time":"2022-02-21T22:39:17Z","timestamp":1645483157000},"page":"454-459","source":"Crossref","is-referenced-by-count":9,"title":["Multi-Precision Deep Neural Network Acceleration on FPGAs"],"prefix":"10.1109","author":[{"given":"Negar","family":"Neda","sequence":"first","affiliation":[{"name":"University of Tehran,Department of Electrical and Computer Engineering,Tehran,Iran"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Salim","family":"Ullah","sequence":"additional","affiliation":[{"name":"Technische Universität Dresden,Department of Computer Science,Dresden,Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Azam","family":"Ghanbari","sequence":"additional","affiliation":[{"name":"University of Tehran,Department of Electrical and Computer Engineering,Tehran,Iran"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hoda","family":"Mahdiani","sequence":"additional","affiliation":[{"name":"University of Tehran,Department of Electrical and Computer Engineering,Tehran,Iran"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mehdi","family":"Modarressi","sequence":"additional","affiliation":[{"name":"University of Tehran,Department of Electrical and Computer Engineering,Tehran,Iran"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Akash","family":"Kumar","sequence":"additional","affiliation":[{"name":"Technische Universität Dresden,Department of Computer Science,Dresden,Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD45719.2019.8942163"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/3373087.3375387"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2017.7927113"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/3289602.3293912"},{"key":"ref14","article-title":"Smapproxlib: library of fpga-based approximate multi-pliers","author":"ullah","year":"2018","journal-title":"Proc of DAC"},{"key":"ref15","article-title":"Area-optimized low-latency approximate multipliers for fpga-based hardware accelerators","author":"ullah","year":"2018","journal-title":"Proc of DAC"},{"key":"ref16","article-title":"Energy-efficient low-latency signed multiplier for fpga-based hardware accelerators","author":"ullah","year":"2020","journal-title":"IEEE Embedded Systems Letters"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA45697.2020.00086"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3123982"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO50266.2020.00062"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2016.7783720"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/3061639.3062307"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TPAMI.2021.3117837"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.18653\/v1\/K18-3013"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1049\/PBCS055E"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2865489"}],"event":{"name":"2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC)","location":"Taipei, Taiwan","start":{"date-parts":[[2022,1,17]]},"end":{"date-parts":[[2022,1,20]]}},"container-title":["2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9712466\/9712479\/09712485.pdf?arnumber=9712485","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,6,20]],"date-time":"2022-06-20T21:17:21Z","timestamp":1655759841000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9712485\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,1,17]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/asp-dac52403.2022.9712485","relation":{},"subject":[],"published":{"date-parts":[[2022,1,17]]}}}