{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,16]],"date-time":"2026-06-16T02:34:43Z","timestamp":1781577283505,"version":"3.54.5"},"reference-count":22,"publisher":"IEEE","license":[{"start":{"date-parts":[[2022,1,17]],"date-time":"2022-01-17T00:00:00Z","timestamp":1642377600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,1,17]],"date-time":"2022-01-17T00:00:00Z","timestamp":1642377600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2022,1,17]]},"DOI":"10.1109\/asp-dac52403.2022.9712562","type":"proceedings-article","created":{"date-parts":[[2022,2,21]],"date-time":"2022-02-21T22:39:17Z","timestamp":1645483157000},"page":"300-306","source":"Crossref","is-referenced-by-count":25,"title":["DREAMPlaceFPGA: An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit"],"prefix":"10.1109","author":[{"given":"Rachel Selina","family":"Rajarathnam","sequence":"first","affiliation":[{"name":"The University of Texas at Austin,Department of Electrical &#x0026; Computer Engineering,TX,USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Mohamed Baker","family":"Alawieh","sequence":"additional","affiliation":[{"name":"The University of Texas at Austin,Department of Electrical &#x0026; Computer Engineering,TX,USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Zixuan","family":"Jiang","sequence":"additional","affiliation":[{"name":"The University of Texas at Austin,Department of Electrical &#x0026; Computer Engineering,TX,USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Mahesh","family":"Iyer","sequence":"additional","affiliation":[{"name":"Intel Corporation,San Jose,CA,USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"David Z.","family":"Pan","sequence":"additional","affiliation":[{"name":"The University of Texas at Austin,Department of Electrical &#x0026; Computer Engineering,TX,USA"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/3233244"},{"key":"ref11","article-title":"DREAMPlace: Deep learning toolkit-enabled GPU acceleration for modern VLSI placement","author":"lin","year":"2020","journal-title":"IEEE Transactions on COMPUTER-AIDED DESIGN of Integrated Circuits and Systems (TCAD)"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/CSTIC49141.2020.9282573"},{"key":"ref13","first-page":"1","article-title":"DREAMPlace 3. 0: multielectrostatics based robust VLSI placement with region constraints","author":"gu","year":"2020","journal-title":"IEEE\/ACM International Conference on Computer Aided Design (IC-CAD)"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/2699873"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/3439706.3446884"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/3388617"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ICEIEC.2017.8076614"},{"key":"ref18","first-page":"8024","article-title":"PyTorch: An Imperative Style, High-Performance Deep Learning Library","author":"paszke","year":"2019","journal-title":"Conference on Neural Information Processing Systems"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2019.00065"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2019.00070"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD45719.2019.8942075"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/NEWCAS.2012.6328998"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/HPEC.2019.8916251"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/HPEC.2018.8547587"},{"key":"ref7","first-page":"1","article-title":"elfPlace: Electrostatics-based Placement for Large-Scale Heterogeneous FPGAs","author":"meng","year":"2021","journal-title":"IEEE Transactions on COMPUTER-AIDED DESIGN of Integrated Circuits and Systems (TCAD)"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2877017"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2905012"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2729349"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/2872334.2886419"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024875"},{"key":"ref21","year":"0","journal-title":"Xilinx Inc"}],"event":{"name":"2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC)","location":"Taipei, Taiwan","start":{"date-parts":[[2022,1,17]]},"end":{"date-parts":[[2022,1,20]]}},"container-title":["2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9712466\/9712479\/09712562.pdf?arnumber=9712562","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,6,13]],"date-time":"2022-06-13T21:08:49Z","timestamp":1655154529000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9712562\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,1,17]]},"references-count":22,"URL":"https:\/\/doi.org\/10.1109\/asp-dac52403.2022.9712562","relation":{},"subject":[],"published":{"date-parts":[[2022,1,17]]}}}