{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T01:15:21Z","timestamp":1740100521995,"version":"3.37.3"},"reference-count":27,"publisher":"IEEE","license":[{"start":{"date-parts":[[2022,1,17]],"date-time":"2022-01-17T00:00:00Z","timestamp":1642377600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,1,17]],"date-time":"2022-01-17T00:00:00Z","timestamp":1642377600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100000006","name":"Office of Naval Research","doi-asserted-by":"publisher","award":["N00014-21-1-2520"],"award-info":[{"award-number":["N00014-21-1-2520"]}],"id":[{"id":"10.13039\/100000006","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2022,1,17]]},"DOI":"10.1109\/asp-dac52403.2022.9712572","type":"proceedings-article","created":{"date-parts":[[2022,2,21]],"date-time":"2022-02-21T22:39:17Z","timestamp":1645483157000},"page":"11-18","source":"Crossref","is-referenced-by-count":0,"title":["SC-K9: A Self-synchronizing Framework to Counter Micro-architectural Side Channels"],"prefix":"10.1109","author":[{"given":"Hongyu","family":"Fang","sequence":"first","affiliation":[{"name":"The George Washington University,Washington, DC,USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Milos","family":"Doroslovacki","sequence":"additional","affiliation":[{"name":"The George Washington University,Washington, DC,USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Guru","family":"Venkataramani","sequence":"additional","affiliation":[{"name":"The George Washington University,Washington, DC,USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","article-title":"Cache template attacks: Automating attacks on inclusive last-level caches","author":"gruss","year":"2015","journal-title":"24th USENIX Security symposium"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/1186736.1186737"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/SP.2019.00002"},{"key":"ref13","article-title":"Meltdown","author":"lipp","year":"2018","journal-title":"ArXiv Preprint"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/SP.2015.43"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2020.2988370"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA47549.2020.00019"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/3352460.3358314"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/1181309.1181317"},{"key":"ref19","article-title":"Foreshadow: Extracting the keys to the Intel SGX kingdom with transient out-of-order execution","author":"van bulck","year":"2018","journal-title":"21th USENIX Security Symposium"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/3296957.3173204"},{"key":"ref27","article-title":"Flush+ reload: a high resolution, low noise, 13 cache side-channel attack","author":"yarom","year":"2014","journal-title":"23rd USENIX Security Symposium"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.42"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2021.3063313"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ACSSC.2018.8645322"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18072.2020.9218725"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1007\/s10766-018-0609-3"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"ref9","first-page":"955","article-title":"Translation leak-aside buffer: Defeating cache side-channel protections with {TLB} attacks","author":"gras","year":"2018","journal-title":"21th USENIX Security Symposium"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA45697.2020.00022"},{"journal-title":"Low-cost and efficient architectural support for correctness and performance debugging","year":"2009","author":"venkataramani","key":"ref20"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2018.00042"},{"journal-title":"System and method for uncovering covert timing channels","year":"2019","author":"venkataramani","key":"ref21"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2019.8740835"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1007\/s10766-018-0608-4"},{"key":"ref26","article-title":"Towards a better indicator for cache timing channels","author":"yao","year":"2019","journal-title":"ArXiv Preprint"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2019.2920814"}],"event":{"name":"2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC)","start":{"date-parts":[[2022,1,17]]},"location":"Taipei, Taiwan","end":{"date-parts":[[2022,1,20]]}},"container-title":["2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9712466\/9712479\/09712572.pdf?arnumber=9712572","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,6,13]],"date-time":"2022-06-13T21:08:34Z","timestamp":1655154514000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9712572\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,1,17]]},"references-count":27,"URL":"https:\/\/doi.org\/10.1109\/asp-dac52403.2022.9712572","relation":{},"subject":[],"published":{"date-parts":[[2022,1,17]]}}}