{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,17]],"date-time":"2026-04-17T16:18:06Z","timestamp":1776442686568,"version":"3.51.2"},"reference-count":60,"publisher":"IEEE","license":[{"start":{"date-parts":[[2022,1,17]],"date-time":"2022-01-17T00:00:00Z","timestamp":1642377600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,1,17]],"date-time":"2022-01-17T00:00:00Z","timestamp":1642377600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2022,1,17]]},"DOI":"10.1109\/asp-dac52403.2022.9712576","type":"proceedings-article","created":{"date-parts":[[2022,2,21]],"date-time":"2022-02-21T17:39:17Z","timestamp":1645465157000},"page":"114-121","source":"Crossref","is-referenced-by-count":15,"title":["Common-Centroid Layout for Active and Passive Devices: A Review and the Road Ahead"],"prefix":"10.1109","author":[{"given":"Nibedita","family":"Karmokar","sequence":"first","affiliation":[{"name":"University of Minnesota,USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Meghna","family":"Madhusudan","sequence":"additional","affiliation":[{"name":"University of Minnesota,USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Arvind K.","family":"Sharma","sequence":"additional","affiliation":[{"name":"University of Minnesota,USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ramesh","family":"Harjani","sequence":"additional","affiliation":[{"name":"University of Minnesota,USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mark Po-Hung","family":"Lin","sequence":"additional","affiliation":[{"name":"National Yang Ming Chiao Tung University,Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sachin S.","family":"Sapatnekar","sequence":"additional","affiliation":[{"name":"University of Minnesota,USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1049\/PBCS003E"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-DAT.2016.7482535"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2013.6691040"},{"key":"ref32","first-page":"289","article-title":"A 10b 200MS\/s 0. 82 mW SAR ADC in 40nm CMOS","author":"huang","year":"2013","journal-title":"Proc A-SSCC"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2042254"},{"key":"ref30","first-page":"70","article-title":"A 0. 3 V 10-bit 1. 17 f SAR ADC with merge and split switching in 90 nm CMOS","volume":"62","author":"lin","year":"2014","journal-title":"IEEE TCAS-I"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2035587"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2687980"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2017.7927277"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2563780"},{"key":"ref60","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2015.7372646"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18072.2020.9218609"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2685598"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2143870"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2005.1465258"},{"key":"ref1","author":"hastings","year":"2001","journal-title":"The Art of Analog Layout"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.2006139"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/SISPAD.2000.871225"},{"key":"ref21","first-page":"171","article-title":"Monte Carlo modeling of threshold variation due to dopant fluctuations","author":"frank","year":"1999","journal-title":"Proc VLSI Symp"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2014.2332264"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1989.572629"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2014.6881492"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2016.2537824"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1145\/2856031"},{"key":"ref51","first-page":"687","article-title":"Gradient sensitivity reduction in current mirrors with non-rectangular layout structures","author":"lan","year":"2000","journal-title":"Proc ISCAS"},{"key":"ref59","doi-asserted-by":"publisher","DOI":"10.1109\/MSSC.2015.2418155"},{"key":"ref58","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.848021"},{"key":"ref57","author":"razavi","year":"2016","journal-title":"Design of Analog CMOS Integrated Circuits"},{"key":"ref56","doi-asserted-by":"publisher","DOI":"10.23919\/DATE51398.2021.9474244"},{"key":"ref55","first-page":"123","article-title":"Analog design challenges and trade-offs using emerging materials and devices","author":"fulde","year":"2007","journal-title":"Proc ESSCIRC"},{"key":"ref54","article-title":"ALIGN: Analog layout, intelligently generated from netlists","year":"0","journal-title":"Software Repository"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2020.3042177"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3323471"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/1123008.1123011"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.884403"},{"key":"ref40","first-page":"1397","article-title":"A new chessboard placement and sizing method for capacitors in a charge-scaling DAC by worst-case analysis of nonlinearity","volume":"35","author":"burcea","year":"2015","journal-title":"IEEE TCAD"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2002.998358"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2204993"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2010.5617407"},{"key":"ref15","first-page":"114t","article-title":"Layout-induced stress effects in 14nm & 10nm FinFETs and their impact on performance","author":"bardon","year":"2013","journal-title":"Proc IEEE Symp On VLSI Technology"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2003.815371"},{"key":"ref17","first-page":"245","article-title":"A scaleable model for STI mechanical stress effect on layout dependence of MOS electrical characteristics","author":"su","year":"2003","journal-title":"Proc CICC"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2006.320869"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD51958.2021.9643532"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2022217"},{"key":"ref3","first-page":"1205","article-title":"Estimation of FMAX and ISB in micro-processors","volume":"13","author":"abulafia","year":"2005","journal-title":"IEEE TVLSI"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2011.2121913"},{"key":"ref5","first-page":"516","article-title":"Modeling within-die spatial correlation effects for process-design co-optimization","author":"friedberg","year":"2005","journal-title":"Proc ISQED"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/43.998626"},{"key":"ref7","first-page":"93","article-title":"Managing process variation in Intel's 45nm CMOS technology","volume":"12","author":"kuhn","year":"2008","journal-title":"Intel Technol J"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2097308"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/66.554480"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2226457"},{"key":"ref45","first-page":"579","article-title":"Analog placement with common centroid constraints","author":"ma","year":"2007","journal-title":"Proc ICCAD"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/SMACD.2017.7981584"},{"key":"ref47","first-page":"1","article-title":"Layout symmetries: Quantification and application to cancel nonlinear process gradients","volume":"36","author":"mcandrew","year":"2016","journal-title":"IEEE TCAD"},{"key":"ref42","first-page":"134","article-title":"PACES: A partition-centering-based symmetry placement for binary-weighted unit capacitor arrays","volume":"36","author":"huang","year":"2016","journal-title":"IEEE TCAD"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1145\/2770872"},{"key":"ref44","article-title":"Constructive common-centroid placement and routing for binary-weighted capacitor arrays","author":"karmokar","year":"2022","journal-title":"Proc DATE"},{"key":"ref43","first-page":"1372","article-title":"PASTEL: Parasitic matching-driven placement and routing of capacitor arrays with generalized ratios in charge-redistribution SAR-ADCs","volume":"39","author":"ding","year":"2019","journal-title":"IEEE TCAD"}],"event":{"name":"2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC)","location":"Taipei, Taiwan","start":{"date-parts":[[2022,1,17]]},"end":{"date-parts":[[2022,1,20]]}},"container-title":["2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9712466\/9712479\/09712576.pdf?arnumber=9712576","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,6,20]],"date-time":"2022-06-20T17:17:25Z","timestamp":1655745445000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9712576\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,1,17]]},"references-count":60,"URL":"https:\/\/doi.org\/10.1109\/asp-dac52403.2022.9712576","relation":{},"subject":[],"published":{"date-parts":[[2022,1,17]]}}}